IP Library Granted Patent US 7,571,397
Granted Patent B2
US 7,571,397 · App. 11/265,040 · Granted Aug 4, 2009

Method of design based process control optimization

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Quick Facts
Patent No.
US 7,571,397
App. No.
11/265,040
Granted
Aug 4, 2009
Kind
B2
Abstract

The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employed to query the circuit layout database to calculate at least one process specification limit. The method includes comparing the calculated at least one process specification limit with at least one predefined technology process tool capability to determine if the calculated at least one process specification limit allows for a manufacturable process. If the calculated at least one process specification limit does not allow for the manufacturable process, the limit may be re-optimized.

Claims (44)

1. A method for design based process control optimization, comprising:

creating, by using a computer, a circuit layout database including a design rule set;

querying by employing at least one algorithm, the circuit layout database to calculate at least one process specification limit;

comparing the calculated at least one process specification limit with at least one predefined technology process to determine if the at least one process specification limit allows for a manufacturable process;

recalculating the at least one process specification limit, if the at least one process specification limit does not allow for the manufacturable process;

performing a manufacturing process step for a semiconductor device according to the at least one process specification limit;

feeding at least one output specification result of the manufacturing process step to a downstream manufacturing process step;

comparing the at least one output specification result of the manufacturing process step with at least one predefined technology process to determine if the at least one output specification result allows for the manufacturable process;

calculating at least one process specification limit for the downstream manufacturing process step, if the at least one output specification result does not allow for the manufacturable process; and

performing a manufacturing process step for a semiconductor device according to the at least one process specification limit for the downstream manufacturing process step.

2. The method as claimed in claim 1 , wherein the manufacturable process is user defined and quantifiable by measurements.

3. The method as claimed in claim 1 , wherein the at least one predefined technology process includes an estimated process tool.

4. The method as claimed in claim 1 , wherein the method for design based process control optimization is employed for semiconductor manufacturing.

5. The method as claimed in claim 1 , further comprising evaluating the at least one process specification limit to determine if the at least one process specification limit complies with a defined design for yield requirement.

6. The method as claimed in claim 1 , wherein the creating a circuit layout database is constructed by use of software.

7. The method as claimed in claim 6 , wherein the software adheres to the design rule set, the design rule set indicating at least one of an allowable feature dimension, an allowable feature spacing, or an allowable feature density.

8. A computer-readable medium having computer-executable instructions for performing a method for design based process control optimization, the method comprising:

creating a circuit layout database including a design rule set;

querying by employing at least one algorithm, the circuit layout database to calculate at least one process specification limit;

comparing the calculated at least one process specification limit with at least one predefined technology process to determine if the at least one process specification limit allows for a manufacturable process;

recalculating the at least one process specification limit, if the at least one process specification limit does not allow for the manufacturable process;

performing a manufacturing process step for a semiconductor device according to the at least one process specification limit;

feeding at least one output specification result of the manufacturing process step to a downstream manufacturing process step;

comparing the at least one output specification result of the manufacturing process step with at least one predefined technology process to determine if the at least one output specification result allows for the manufacturable process;

calculating at least one process specification limit for the downstream manufacturing process step, if the at least one output specification result does not allow for the manufacturable process; and

performing a manufacturing process step for a semiconductor device according to the at least one process specification limit for the downstream manufacturing process step.

9. The computer-readable medium as claimed in claim 8 , wherein the manufacturable process is user defined and quantifiable by measurements.

10. The computer-readable medium as claimed in claim 8 , wherein the at least one predefined technology process includes an estimated process tool capability.

11. The computer-readable medium as claimed in claim 8 , wherein the method for design based process control optimization is employed for semiconductor manufacturing.

12. The computer-readable medium as claimed in claim 8 , wherein the method further comprises evaluating the at least one process specification limit to determine if the at least one process specification limit complies with a defined design for yield requirement.

13. The computer-readable medium as claimed in claim 8 , wherein the design rule set indicates at least one of an allowable feature dimension, an allowable feature spacing, or an allowable feature density.

14. A method for design based process control optimization, comprising:

creating, by using a computer, a design rule set, the design rule set including at least one technology process requirement, manufacturing requirement or design for yield requirement;

employing at least one algorithm to query the design rule set to calculate at least one process specification limit;

comparing the at least one process specification limit with the at least one technology process requirement, manufacturing requirement, or design for yield requirement to determine if the at least one process specification limit complies with the at least one technology process requirement, manufacturing requirement, or design for yield requirement;

recalculating the at least one process specification limit, if the at least one process specification limit does not comply with the at least one technology process requirement, manufacturing requirement, or design for yield requirement

performing a manufacturing process step for a device according to the at least one process specification limit;

feeding at least one output specification result of the manufacturing process step to a downstream manufacturing process step;

comparing the at least one output specification result of the manufacturing process step with a second at least one technology process requirement, manufacturing requirement, or design for yield requirement to determine if the at least one output specification result complies with the second at least one technology process requirement, manufacturing requirement, or design for yield requirement;

calculating at least one process specification limit for the downstream manufacturing process step, if the at least one output specification result does not comply with the second at least one technology process requirement, manufacturing requirement, or design for yield requirement; and

performing a second manufacturing process step for the device according to the at least one process specification limit for the downstream manufacturing process step.

15. The method for design based process control optimization as claimed in claim 14 , wherein the design rule set includes at least one device specific process requirement.

16. The method for design based process control optimization as claimed in 15 , further comprising comparing the at least one process specification limit with the at least one device specific process requirement.

17. The method for design based process control optimization as claimed in claim 14 , wherein the method for design based process control optimization is employed for semiconductor manufacturing.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2005
From: HANSON, JEFFREY; GIEWONT, MARK A.
To: LSI LOGIC CORPORATION
Reel/Frame 017187/0715 →