IP Library Granted Patent US 7,220,362
Granted Patent B2
US 7,220,362 · App. 11/337,460 · Granted May 22, 2007

Planarization with reduced dishing

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 7,220,362
App. No.
11/337,460
Granted
May 22, 2007
Kind
B2
Abstract

A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Claims (11)

1. A method of forming a planarized layer on a substrate, the method comprising the steps of:

cleaning the substrate,

forming the layer having a surface with relatively high portions and relatively low portions,

forming a resistive mask over the relatively high portions of the layer and not over the relatively low portions of the layer,

treating the surface of the layer to make it more resistive to planarization, where the relatively low portions of the layer are exposed to the treatment and the relatively high portions of the layer underlying the resistive mask are not exposed to the treatment,

removing the resistive mask from the surface of the layer, and

planarizing the surface of the layer, where the relatively high portions of the layer are eroded at a first rate and the relatively low portions of the layer are eroded at a second rate that is less than the first rate due to the treatment received by the relatively low portions of the layer, to provide a planarized layer.

2. The method of claim 1 , wherein the step of treating the surface of the layer comprises implanting at least one of carbon, nitrogen, tantalum, tantalum nitride, titanium, and titanium nitride.

3. The method of claim 1 , wherein the step of treating the surface of the layer comprises plasma treatment with at least one of carbon, nitrogen, tantalum, tantalum nitride, titanium, and titanium nitride.

4. The method of claim 1 , wherein the layer is a copper layer.

5. The method of claim 1 , wherein the step of planarizing the surface comprises at least one of chemical mechanical polishing the surface and electropolishing the surface.

Assignments (10)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (2)
Division 1042106800 · Apr 23, 2003
Related Publication 20060118523A1 · Jun 8, 2006