Control of hot carrier injection in a metal-oxide semiconductor device
View Patent ↗In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.
1. In a metal-oxide semiconductor device comprising first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device, the method comprising the steps of:
forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region;
adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation subject to a constraint that a breakdown voltage in the device be greater than or equal to a prescribed value wherein the shielding structure is spaced laterally from the gate and is configured to overlap at least an edge of the gate.
2. The method of claim 1 , further comprising the step of measuring a percentage increase in on-resistance in the device, the percentage increase in on-resistance being indicative of the amount of hot-carrier injection degradation in the device.
3. The method of claim 2 , wherein the shielding structure is formed having an amount of coverage over an upper surface of the drift region configured to produce a percentage increase in on-resistance in the MOS device according to an expression:
% Increase in R ON =a ·(% Shielding Structure Coverage)+ b,
where % Increase in R ON is the percentage increase in on-resistance in the device, % Shielding Structure Coverage is the amount of coverage of the shielding structure over the upper surface of the drift region, a is a first prescribed parameter relating to at least one physical factor of the device, and b is a second prescribed parameter relating to at least one process factor used to form the device.
4. The method of claim 2 , wherein the shielding structure is formed such that the amount of coverage of the shielding structure over the upper surface of the drift region is configured to produce an increase in on-resistance in the device which is in a range from about 0.8 percent to about 4.8 percent.
5. The method of claim 1 , further comprising the step of measuring an initial peak substrate current in the device, the initial peak substrate current being indicative of the amount of hot-carrier injection degradation in the device.
6. The method of claim 1 , wherein the amount of coverage of the shielding structure over the drift region is at least about ten percent of the upper surface of the drift region.
7. The method of claim 1 , wherein the amount of coverage of the shielding structure over the drift region is in a range from about 10 percent to about 40 percent of the upper surface of the drift region.
8. The method of claim 1 , wherein the shielding structure is spaced laterally from the gate and is configured to be in a substantially non-overlapping arrangement relative to the gate.
9. The method of claim 1 , further comprising the step of controlling a shape of the shielding structure so as to control an electric field distribution in at least the drift region and to reduce hot-carrier injection degradation in the metal-oxide semiconductor device.
10. The method of claim 9 , wherein the shape of the shielding structure is configured so that the electric field is substantially uniformly distributed in at least the drift region of the metal-oxide semiconductor device.
11. The method of claim 1 , further comprising the step of electrically connecting the shielding structure to the first source/drain region.
12. The method of claim 1 , further comprising the steps of:
forming a first portion of the insulating layer under the gate to have a first thickness; and
forming a second portion of the insulating layer under the shielding structure to have a second thickness, the first thickness being different in comparison to the second thickness.
13. The method of claim 1 , wherein the prescribed value of the breakdown voltage is at least equal to about 75 volts.
14. In a metal-oxide semiconductor device comprising first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device, the method comprising the steps of:
forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region, the shielding structure being spaced laterally from the gate and overlapping at least an edge of the gate;
adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to produce a peak substrate current in the MOS device less than about 70 microamperes subject to a constraint that a breakdown voltage in the device be greater than about 75 volts, such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of the amount of coverage of the shielding structure over the upper surface of the drift region wherein the shielding structure is spaced laterally from the gate and is configured to overlap at least an edge of the gate.