IP Library Granted Patent US 7,804,291
Granted Patent B2
US 7,804,291 · App. 11/673,714 · Granted Sep 28, 2010

Semiconductor test device with heating circuit

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 7,804,291
App. No.
11/673,714
Granted
Sep 28, 2010
Kind
B2
Abstract

A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

Claims (34)

1. A method comprising the steps of:

forming a semiconductor device including an integrated test circuit and a heating element, wherein the heating element includes a plurality of circuit meanders, one or more first meanders positioned in a horizontal plane around a test circuit, and one or more second meanders in a vertical plane around the test circuit, wherein the one or more first meanders and the one or more second meanders surround the test circuit within a three-dimensional space;

applying power to the heating element to provide heating of the test circuit;

applying power to the test circuit; and

measuring an electrical parameter of the test circuit, wherein the electrical parameter is related to the temperature of the test circuit.

2. The method of claim 1 , wherein the step of applying power to the heating element comprises:

applying AC power to the heating element to provide controlled heating of the test circuit with a current so as to substantially avoid electromigration in the heating element whereby the heating element is operated at a temperature exceeding a standard operating temperature of the semiconductor device and whereby the characteristics of the AC power are controlled by a controller.

3. The method of claim 2 , wherein the step of applying power to the test circuit comprises:

applying DC power to the test circuit and measuring an electrical parameter of the test circuit, wherein the DC power is applied to the test circuit from a source separate from a source of the AC power.

4. The method of claim 2 , wherein the AC power is turned on and off at a predetermined rate to expose the test circuit to temperature cycling.

5. A method of testing a semiconductor fabrication process, the method comprising the steps of:

forming a semiconductor device including an integrated test circuit and a heating element, wherein the heating element includes a plurality of circuit meanders, one or more first meanders positioned in a horizontal plane around a test circuit, and one or more second meanders in a vertical plane around the test circuit, wherein the one or more first meanders and the one or more second meanders surround the test circuit within a three-dimensional space;

applying power to the heating element to provide heating of the test circuit, wherein the applied power is AC power with a current so as to substantially avoid electromigration in the heating element, whereby the heating element is operated at a temperature exceeding a standard operating temperature of the semiconductor device and whereby the characteristics of the AC power are controlled by a controller; and

applying power to the test circuit;

measuring an electrical parameter of the test circuit, wherein the electrical parameter is related to the temperature of the test circuit.

6. A semiconductor test apparatus comprising:

a heating element including a plurality of circuit meanders, one or more first meanders positioned in a horizontal plane around a test circuit, and one or more second meanders in a vertical plane around the test circuit, wherein the one or more first meanders and the one or more second meanders surround the test circuit within a three-dimensional space;

a first power supply for applying power to the heating element to provide heating of the test circuit;

a second power supply for applying power to the test circuit; and

a test device for measuring an electrical parameter of the test circuit, wherein the electrical parameter is related to the temperature of the test circuit.

7. The invention of claim 6 , wherein the first power supply comprises:

an AC power supply for providing power to the heating element to provide controlled heating of the test circuit with a current so as to substantially avoid electromigration in the heating element, whereby the heating element is operated at a temperature exceeding a standard operating temperature of the semiconductor device and whereby the characteristics of the AC power are controlled by a controller.

8. The invention of claim 7 , wherein the second power supply comprises:

a DC power supply for applying DC power to the test circuit.

9. The invention of claim 7 , wherein the AC power supply is turned on and off at a predetermined rate to expose the test circuit to temperature cycling.

10. A method comprising the steps of:

forming a semiconductor device including an integrated test circuit and a heating element, wherein the heating element includes a plurality of circuit meanders, one or more first meanders positioned in a horizontal plane around a test circuit, and one or more second meanders in a vertical plane around the test circuit, wherein the one or more first meanders and the one or more second meanders surround the test circuit within a three-dimensional space;

applying AC power to the heating element to provide controlled heating of the test circuit with a current so as to substantially avoid electromigration in the heating element, whereby the heating element is operated at a temperature exceeding a standard operating temperature of the semiconductor device applying power to the test circuit and whereby the characteristics of the AC power are controlled by a controller; and

measuring an electrical parameter of the test circuit, wherein the electrical parameter is related to the temperature of the test circuit.

11. A semiconductor test apparatus comprising:

a heating element including a plurality of circuit meanders, one or more first meanders positioned in a horizontal plane around a test circuit, and one or more second meanders in a vertical plane around the test circuit, wherein the one or more first meanders and the one or more second meanders surround the test circuit within a three-dimensional space;

an AC power supply for providing power to the heating element to provide controlled heating of the test circuit with a current so as to substantially avoid electromigration in the heating element, whereby the heating element is operated at a temperature exceeding a standard operating temperature of the semiconductor device and whereby the characteristics of the AC power are controlled by a controller;

a second power supply for applying power to the test circuit; and

a test device for measuring an electrical parameter of the test circuit, wherein the electrical parameter is related to the temperature of the test circuit.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (2)
Continuation 1095245300 · Sep 28, 2004
Related Publication 20070168818A1 · Jul 19, 2007