High throughput pipelined data path
View Patent ↗Methods and apparatus to provide a high throughput pipelined data path are described. In one embodiment, an apparatus may include three stages to process inbound data packets, e.g., to align one or more bits of data. Other embodiments are also described.
1. An apparatus comprising:
a first stage to receive a plurality of data packets, comprising a data packet, through a physical interface, wherein the first stage is to load data corresponding to the received packet in response to a determination that the received packet is a valid expected completion packet with a valid destination;
a second stage to determine whether one or more bits within the data packet are to be shifted and align the bits;
a third stage coupled to a transfer interface to transfer the aligned bits; and
a storage device to store a plurality of entries to indicate read completion status corresponding to the plurality of data packets, wherein a buffer stores data corresponding to the data packet to stall a next transfer received at the first stage for one or more clock cycles in response to a determination that it will take two backend transfers to complete a single frontend transfer of the data packet.
2. The apparatus of claim 1 , wherein the second stage computes a byte count, shift count, first byte enable, and last byte enable.
3. The apparatus of claim 1 , wherein the second stage computes the shift count based on a group consisting essentially of source and destination addresses of the data packet.
4. The apparatus of claim 1 , wherein a network interface card comprises the first, second, and third stages.
5. The apparatus of claim 1 , wherein the physical interface is coupled to a network.
6. The apparatus of claim 1 , wherein the transfer interface is coupled to a host computer.
7. The apparatus of claim 1 , wherein the read completion status is to indicate whether a corresponding data packet from the plurality of data packets has been completely received at the first stage.
8. A method comprising:
receiving at a first stage a plurality of data packets, comprising a data packet, wherein the first stage is to load data corresponding to the received packet in response to a determination that the received packet is a valid expected completion packet with a valid destination;
determining at a second stage whether one or more bits within the data packet are to be shifted and align the bits;
transferring at a third stage the aligned bits; and
storing a plurality of entries to indicate read completion status corresponding to the plurality of data packets, wherein a buffer stores data corresponding to the data packet to stall a next transfer received at the first stage for one or more clock cycles in response to a determination that it will take two backend transfers to complete a single frontend transfer of the data packet.
9. The method of claim 8 , further comprising receiving the data packet through a physical interface.
10. The method of claim 8 , further comprising coupling the third stage to a transfer interface to transfer the aligned bits.
11. The method of claim 10 , further comprising coupling the transfer interface to a host computer.
12. The method of claim 8 , further comprising the second stage computing a byte count, shift count, first byte enable, and last byte enable of the received data packet.
13. The method of claim 8 , further comprising the second stage computing the shift count based on a group consisting essentially of source and destination addresses of the data packet.
14. The method of claim 8 , wherein the read completion status is to indicate whether a corresponding data packet from the plurality of data packets has been completely received at the first stage.
15. A computer-readable storage medium storing one or more instructions that when executed on a processor configure the processor to:
receive at a first stage a plurality of data packets, comprising a data packet, wherein the first stage is to load data corresponding to the received packet in response to a determination that the received packet is a valid expected completion packet with a valid destination;
determine at a second stage whether one or more bits within the data packet are to be shifted and align the bits;
transfer at a third stage the aligned bits; and
store a plurality of entries to indicate read completion status corresponding to the plurality of data packets, wherein a buffer stores data corresponding to the data packet to stall a next transfer received at the first stage for one or more clock cycles in response to a determination that it will take two backend transfers to complete a single frontend transfer of the data packet.
16. The computer-readable storage medium of claim 15 , further comprising one or more instructions that configure the processor to receive the data packet through a physical interface.
17. The computer-readable storage medium of claim 15 , further comprising one or more instructions that configure the processor to cause the second stage to compute a byte count, shift count, first byte enable, and last byte enable of the received data packet.
18. The computer-readable storage medium of claim 15 , wherein the read completion status is to indicate whether a corresponding data packet from the plurality of data packets has been completely received at the first stage.