Secure, stable on chip silicon identification
A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.
1. A circuit for providing a bit string, the circuit comprising:
a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string,
an enable line associated with each of the bit cells,
each enable line having a fuse adapted to be activated upon application of a signal by a tester,
each bit cell configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated, and
the circuit adapted such that bit cells having fuses that are activated are logically removed from the bit string.
2. The circuit of claim 1 , wherein the bit string comprises an identification string.
3. The circuit of claim 1 , wherein the bit string comprises an encryption key.
4. The circuit of claim 1 , wherein the fuse is a polysilicon fuse that is open-circuited upon application of the signal by the tester.
5. The circuit of claim 1 , wherein the fuse is an antifuse that is close-circuited upon application of the signal by the tester.
6. An integrated circuit having a circuit for providing a bit string, the circuit comprising:
a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string,
an enable line associated with each of the bit cells,
each enable line having a fuse adapted to be activated upon application of a signal by a tester,
each bit cell configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated, and
the circuit adapted such that bit cells having fuses that are activated are logically removed from the bit string.
7. The integrated circuit of claim 6 , wherein the bit string comprises an identification string.
8. The integrated circuit of claim 6 , wherein the bit string comprises an encryption key.
9. The integrated circuit of claim 6 , wherein the fuse is a polysilicon fuse that is open-circuited upon application of the signal by the tester.
10. The integrated circuit of claim 6 , wherein the fuse is an antifuse that is close-circuited upon application of the signal by the tester.
11. A method for providing a bit string, the method comprising the steps of:
providing a specified input to a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon the specified input, and each bit cell comprises a bit in the bit string,
detecting the bit cells that do not consistently provide only one of a logical high and a logical low upon the specified input, designated as soft cells,
logically isolating the soft cells by activating a separate fuse associated with each soft cell with a signal from a tester, and
logically removing from the bit string all the soft cells with activated fuses.
12. The method of claim 11 , wherein the bit string comprises an identification string.
13. The method of claim 11 , wherein the bit string comprises an encryption key.
14. The method of claim 11 , wherein the fuse is a polysilicon fuse that is open-circuited upon application of the signal by the tester.
15. The method of claim 11 , wherein the fuse is an antifuse that is close-circuited upon application of the signal by the tester.