Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction
View Patent ↗A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y 1 . A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y 2 . The path slack calculated for the setup timing check and for the hold timing check is generated as output.
1. A method of static timing analysis comprising steps of:
receiving as input minimum and maximum stage delays for two corners of an integrated circuit design;
calculating path slack for a setup timing check from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y 1 ;
calculating path slack for a hold timing check from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y 2 ; and
generating as output the path slack calculated for the setup timing check and for the hold timing check.
2. The method of claim 1 further comprising calculating T_CP from the formula (1−Y 1 )*(min 1 _wc+min 3 _wc), where min 1 _wc is a minimum worst case delay for a common path segment, and min 3 _wc is a minimum worst case incremental capture path delay.
3. The method of claim 2 further comprising calculating T_LP from the formula (max 1 _wc+max 2 _wc), where max 1 _wc is a maximum worst case delay for a common path segment, and max 2 _wc is a maximum worst case incremental launch path delay.
4. The method of claim 3 further comprising setting T_DP equal to max 4 _wc, where max 4 _wc is a maximum worst case data path delay.
5. The method of claim 4 further comprising calculating path slack for the setup timing check from the formula (T_clk+T_CP−T_LP−T_DP).
6. The method of claim 1 further comprising calculating T_CP from the formula (min 1 _bc+min 3 _bc), where min 1 _bc is a minimum best case delay for a common path segment, and min 3 _bc is a minimum best case incremental capture path delay.
7. The method of claim 6 further comprising calculating T_LP from the formula (1+Y 1 )*(max 1 _bc+max 2 _bc), where max 1 _bc is a maximum best case delay for a common path segment, and max 2 _bc is a maximum best case incremental launch path delay.
8. The method of claim 7 further comprising calculating T_DP from the formula (1+Y 1 )*max 4 _bc, where max 4 _bc is a maximum best case data path delay.
9. The method of claim 8 further comprising calculating path slack for the setup timing check from the formula (T_clk+T_CP−T_LP−T_DP).
10. The method of claim 1 further comprising calculating T_CP from the formula (max 1 _wc+max 3 _wc), where max 1 _wc is a maximum worst case delay for a common path segment, and max 3 _wc is a maximum worst case incremental capture path delay.
11. The method of claim 10 further comprising calculating T_LP from the formula (max 1 _wc+(1−Y 2 )* min 2 _wc), where max1_wc is a maximum worst case delay for a common path segment, and min 2 _wc is a minimum worst case incremental launch path delay.
12. The method of claim 11 further comprising calculating T_DP from the formula (1−Y 1 )*min 4 _wc, where min 4 _wc is a minimum worst case data path delay.
13. The method of claim 12 further comprising calculating path slack for the hold timing check from the formula (T_LP+T_DP−T_CP).
14. The method of claim 1 further comprising calculating T_CP from the formula (min 1 _bc+(1+Y 1 )* max 3 _bc), where min 1 _wc is a minimum worst case delay for a common path segment, and max 3 _bc is a maximum best case incremental capture path delay.
15. The method of claim 14 further comprising calculating T_LP from the formula (min 1 _bc+min 2 _bc), where min 1 _bc is a minimum best case delay for a common path segment, and min 2 _bc is a minimum best case incremental launch path delay.
16. The method of claim 15 further comprising setting T_DP equal to min 4 _bc, where min 4 _bc is a minimum best case data path delay.
17. The method of claim 16 further comprising calculating path slack for the hold timing check from the formula (T_LP+T_DP−T_CP).
18. A computer program product for optimizing register transfer level code for an integrated circuit design comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:
receiving as input minimum and maximum stage delays for two corners of an integrated circuit design;
calculating path slack for a setup timing check from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y 1 ;
calculating path slack for a hold timing check from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y 2 ; and
generating as output the path slack calculated for the setup timing check and for the hold timing check.
19. The computer program product of claim 18 further comprising calculating T_CP from the formula (1−Y 1 )*(min 1 _wc+min 3 _wc), where min 1 _wc is a minimum worst case delay for a common path segment, and min 3 _wc is a minimum worst case incremental capture path delay.
20. The computer program product of claim 19 comprising calculating T_LP from the formula (max 1 _wc+max 2 _wc), where max 1 _wc is a maximum worst case delay for a common path segment, and max 2 _wc is a maximum worst case incremental launch path delay.
21. The computer program product of claim 20 further comprising setting T_DP equal to max 4 _wc, where max 4 _wc is a maximum worst case data path delay.
22. The computer program product of claim 21 further comprising calculating path slack for the setup timing check from the formula (T_clk+T_CP−T_LP−T_DP).
23. The computer program product of claim 18 further comprising calculating T_CP from the formula (min 1 _bc+min 3 _bc), where min 1 _bc is a minimum best case delay for a common path segment, and min 3 _bc is a minimum best case incremental capture path delay.
24. The computer program product of claim 23 further comprising calculating T_LP from the formula (1+Y 1 )*(max 1 _bc+max 2 _bc), where max 1 _bc is a maximum best case delay for a common path segment, and max 2 _bc is a maximum best case incremental launch path delay.
25. The computer program product of claim 24 further comprising calculating T_DP from the formula (1+Y 1 )*max 4 _bc, where max 4 _bc is a maximum best case data path delay.
26. The computer program product of claim 25 further comprising calculating path slack for the setup timing check from the formula (T_clk+T_CP−T_LP−T_DP).
27. The computer program product of claim 18 further comprising calculating T_CP from the formula (max 1 _wc+max 3 _wc), where max 1 _wc is a maximum worst case delay for a common path segment, and max 3 _wc is a maximum worst case incremental capture path delay.
28. The computer program product of claim 27 further comprising calculating T_LP from the formula (max 1 _wc+(1−Y 2 )*min 2 _wc), where max 1 _wc is a maximum worst case delay for a common path segment, and min 2 _wc is a minimum worst case incremental launch path delay.
29. The computer program product of claim 27 comprising calculating T_DP from the formula (1−Y 2 )* min 4 _wc, where min 4 _wc is a minimum worst case data path delay.
30. The computer program product of claim 29 further comprising calculating path slack for the hold timing check from the formula (T_LP+T_DP−T_CP).
31. The computer program product of claim 18 further comprising calculating T_CP from the formula (min 1 _bc+(1+Y 2 )*max 3 _bc), where min 1 _wc is a minimum worst case delay for a common path segment, and max 3 _bc is a maximum best case incremental capture path delay.
32. The computer program product of claim 31 further comprising calculating T_LP from the formula (min 1 _bc+min 2 _bc), where min 1 _bc is a minimum best case delay for a common path segment, and min 2 _bc is a minimum best case incremental launch path delay.
33. The computer program product of claim 32 further comprising setting T_DP equal to min 4 _bc, where min 4 _bc is a minimum best case data path delay.
34. The computer program product of claim 33 further comprising calculating path slack for the hold timing check from the formula (T_LP+T_DP−T_CP).