Method and apparatus for booting independent operating systems in a multi-processor core integrated circuit

1. A boot process comprising:

a) executing boot load instructions stored in non-volatile memory by each of first and second processors embedded on the same integrated circuit;

b)1) prior to step c), placing the first processor in a first processor loop in response to the instructions until the second processor rings a first processor doorbell;

b)2) placing the second processor in a second processor loop in response to the instructions and ringing the first processor doorbell when the second processor is in the second processor loop;

b)3) releasing the first processor from the first processor loop after the first processor doorbell has been rung in step b)2);

c) executing an initialization procedure for the integrated circuit by the first processor in response to the instructions;

d) ringing a second processor doorbell upon completion of at least a portion of the initialization procedure; and

e) releasing the second processor from the second processor loop after the second processor doorbell has been rung.

2. The boot process of claim 1 wherein upon reset of the integrated circuit, the first and second processors have a memory map such that each processor begins executing the boot load instructions from the same address location in the non-volatile memory in step a).

3. The boot process of claim 1 wherein after completion of at least a portion of the initialization procedure in step c), the first and second processors have respective, unique memory maps that each include a respective memory area within a volatile memory for the first and second processors.

4. The boot process of claim 3 and further comprising:

after step d), for each of the first and second processors, jumping to instructions stored in the respective memory area for that processor.

5. The boot process of claim 1 wherein the second processor executes the second processor loop entirely from a respective instruction cache of the second processor.

6. The boot process of claim 1 and further comprising:

f) prior to step d), in response to the boot load instructions executed by the first processor, copying first and second boot procedure instructions for the first and second processors, respectively, from the non-volatile memory to respective memory areas for the first and second processors within a volatile memory.

7. The boot procedure of claim 6 and further comprising:

g) after ringing the second processor doorbell in step d), within a sequence of the boot load instructions executed by the first processor, jumping to the first boot procedure instructions within the respective memory area in the volatile memory for the first processor; and

h) after releasing the second processor from the second processor loop in step e), within a sequence of the boot load instructions executed by the second processor, jumping to the second boot procedure instructions within the respective memory area in the volatile memory for the second processor.

8. The boot procedure of claim 7 and further comprising:

i) in response to execution of the first and second boot procedure instructions by the first and second processors, copying first and second operating systems from the non-volatile memory to the respective memory areas in the volatile memory for the first and second processors.

9. The boot process of claim 1 and further comprising:

f) prior to step d), in response to the boot load instructions executed by the first processor, remapping an address location of the non-volatile memory from an initial address location to a different address location within a respective memory map for each of the first and second processors.

10. A multiple-processor system comprising:

an integrated circuit comprising first and second independent, embedded processors;

a volatile memory, which is shared by the first and second processors;

a non-volatile memory, which is shared by the first and second processors and comprises a set of boot load instructions executable by the first and second processors;

a reset state in which the first and second processors have respective memory maps such that each processor begins executing the boot load instructions from the same address location in the non-volatile memory upon exit from the reset state; and

a booted state in which the each of the respective memory maps have been uniquely remapped relative to the reset state such that each processor comprises a respective memory area within the volatile memory, which contains a respective set of further instructions for execution by that processor.

11. The multiple-processor system of claim 10 wherein the boot load instructions comprise:

a) instructions that place the second processor in a second processor loop until the first processor rings a second processor doorbell;

b) instructions executable by the first processor that perform an initialization procedure for the integrated circuit;

c) instructions that ring the second processor doorbell upon completion of at least a portion of the initialization procedure; and

d) instructions executable by the second processor that release the second processor from the second processor loop after the second processor doorbell has been rung.

12. The multiple-processor system of claim 11 and further comprising:

e) instructions that cause the first processor to jump to the respective set of further instructions stored in the respective memory area in the volatile memory for the first processor, after execution of the instructions in c); and

f) instructions that cause the second processor to jump to the respective set of further instructions stored in the respective memory area in the volatile memory for the second processor, after execution of the instructions in d).

13. The multiple-processor system of claim 11 wherein the instructions in a) comprise:

a)1) instructions executed by the first processor prior to execution of the instructions in b) and place the first processor in a first processor loop until the second processor rings a first processor doorbell;

a)2) instructions executed by the second processor that place the second processor in the second processor loop and ring the first processor doorbell when the second processor is in the second processor loop; and

a)3) instructions that release the first processor from the first processor loop after the first processor doorbell has been rung in step a)2).

14. The multiple-processor system of claim 11 wherein the second processor comprises an instruction cache and the second processor executes instructions, which perform the second processor loop, entirely from the instruction cache.

15. The multiple-processor system of claim 11 and further comprising:

e) instructions executed by the first processor prior to the instructions in c) that copy first and second boot procedure instructions for the first and second processors, respectively, from the non-volatile memory to the respective memory areas for the first and second processors within the volatile memory.

16. The multiple-processor system of claim 15 and further comprising:

f) instructions executable by the first processor after ringing the second processor doorbell in c) that jump to the first boot procedure instructions within the respective memory area in the volatile memory for the first processor; and

g) instructions executable by the first processor after the second processor is released from the second processor loop in d) that jump to the second boot procedure instructions within the respective memory area in the volatile memory for the second processor.

17. The multiple-processor system of claim 16 wherein the first and second boot procedure instructions comprise respective instructions that, when executed by the first and second processors, respectively, copy first and second operating systems from the non-volatile memory to the respective memory areas in the volatile memory for the first and second processors.

18. The multiple-processor system of claim 11 and further comprising:

e) instructions executable by the first processor prior to the instructions in c) that remap an address location of the non-volatile memory from an initial address location to a different address location within a respective memory map for each of the first and second processors.

19. A multiple-processor system comprising:

an integrated circuit comprising first and second independent, embedded processors;

a volatile memory; and

a non-volatile memory, which comprises a set of boot load instructions comprising:

a) instructions that place the first processor in a first processor loop until the second processor rings a first processor doorbell;

b) instructions that place the second processor in a second processor loop and ring the first processor doorbell when the second processor is in the second processor loop;

c) instructions that release the first processor from the first processor loop after the first processor doorbell has been rung;

d) instructions executable by the first processor after step c) that perform an initialization procedure for the integrated circuit;

e) instructions that ring a second processor doorbell upon completion of at least a portion of the initialization procedure; and

f) instructions executable by the second processor that release the second processor from the second processor loop after the second processor doorbell has been rung.