IP Library Granted Patent US 7,397,295
Granted Patent B2
US 7,397,295 · App. 11/345,929 · Granted Jul 8, 2008

Active current cancellation for high performance video clamps

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,397,295
App. No.
11/345,929
Granted
Jul 8, 2008
Kind
B2
Abstract

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.

Claims (33)

1. An apparatus comprising:

a first circuit configured to generate a video input signal having a voltage;

a second circuit having a finite input resistance configured to generate a first current in response to applying said voltage across said finite input resistance, and

a third circuit to (a) receive said voltage and (b) cancel said current by generating a second current having a negative value when compared with said first current, wherein said second current is generated in response to applying said voltage across a replica resistor having a resistance similar to said finite input resistance.

2. The apparatus according to claim 1 , wherein said third circuit further comprises:

a first operational amplifier to (i) duplicate said voltage generated in said first circuit and (ii) present said voltage to said replica resistor; and

one or more current sources configured to pass said current away from said apparatus.

3. The apparatus according to claim 2 , wherein said third circuit further comprises a first transistor, a second transistor and a third transistor, wherein said second transistor and said third transistor form a current mirror circuit.

4. The apparatus according to claim 3 , wherein (i) said first transistor is an N-type transistor, (ii) said second transistor is a P-type transistor and (iii) said third transistor is a P-type transistor.

5. The apparatus according to claim 2 , wherein said one or more current sources include a first current source and a second current source.

6. The apparatus according to claim 1 , wherein said first circuit further comprises a second operational amplifier, a first resistor and a second resistor.

7. The apparatus according to claim 6 , wherein said operational amplifier, said first resistor and said second resistor are implemented as an inverted operational amplifier circuit to provide linear and high bandwidth properties for said apparatus.

8. The apparatus according to claim 6 , where said second resistor is a variable resistor.

9. The apparatus according to claim 1 , further comprising:

a clamp circuit to restore a DC level of a portion of said video input signal to a predetermined value.

10. The apparatus according to claim 1 , wherein said apparatus is implemented in a system selected from the group consisting of video clamps and instrumentation amplifiers.

11. An apparatus comprising:

a first circuit configured to generate a video input signal having a voltage;

a second circuit having a finite input resistance configured to generate a first current in response to applying said voltage across said finite input resistance, and

a third circuit to (i) divide said voltage into a predetermined voltage level with a high impedance divider and (ii) cancel said current by generating a second current having a negative value when compared to said first current, in response to applying said predetermined voltage level across a replica resistor.

12. The apparatus according to claim 11 , wherein said high impedance divider comprises one or more resistors.

13. The apparatus according to claim 12 , wherein said third circuit further comprises a first operational amplifier coupled to said one or more resistors.

14. The apparatus according to claim 12 , wherein said replica resistor includes a resistance which is proportional to said finite input resistance.

15. The apparatus according to claim 13 , wherein said third circuit further comprises a first transistor, a second transistor and a third transistor, wherein said second transistor and said third transistor form a current mirror circuit.

16. The apparatus according to claim 15 , wherein (i) said first transistor is an N-type transistor, (ii) said second transistor is a P-type transistor and (iii) said third transistor is a P-type transistor.

17. The apparatus according to claim 11 , wherein said third circuit comprises one or more current sources configured to pass said current away from said apparatus.

18. The apparatus according to claim 11 , wherein said first circuit further comprises a second operational amplifier, a first resistor and a second resistor.

19. The apparatus according to claim 18 , wherein said second operational amplifier, said first resistor and said second resistor are implemented as an inverted operational amplifier circuit to provide linear and high bandwidth properties for said apparatus.

20. A method for actively canceling a current for high performance video clamps:

(A) generating a video input signal having a voltage;

(B) providing a finite input resistance to generate a first current in response to presenting said voltage across said finite input resistance;

(C) generating a second current having a negative value when compared with said first current in response to presenting said voltage across a replica resistor having a resistance similar to said finite input resistance; and

(D) canceling said current in response to performing steps (A)-(C).

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →