Hybrid multiple bit-depth video processing architecture
View Patent ↗An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.
1. An apparatus comprising:
a processor configured to
(a) process pixel data comprising eight or more bits, wherein for pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of said pixel are packed with LSBs from one or more other pixels into a second byte, and the first and the second bytes are stored,
(b) retrieve said first byte and said second byte and reassemble the pixel data having bit-depths greater than eight bits from said first byte and said second byte,
(c) retrieve the stored first bytes, generate a compressed bitstream using only the first bytes, and store said compressed bitstream, wherein said compressed bitstream comprises at least one of (i) a MPEG-2 compliant compressed bitstream, (ii) a MPEG-4 compliant compressed bitstream, and (iii) a H.264 compliant compressed bitstream,
(d) retrieve said compressed bitstream and generate a multi-bit data stream having a bit-depth greater than eight bits using said compressed bitstream, and
(e) generate a video output signal in response to (i) the original pixel data in a first mode, (ii) the reassembled pixel data in a second mode, and (iii) the multi-bit data stream in a third mode; and
a memory coupled to said processor and configured to store said first byte in response to a first pointer and said second byte in response to a second pointer, wherein said first byte and said second byte are stored independently in said memory and said memory is further configured to store said compressed bitstream.
2. The apparatus according to claim 1 , wherein said apparatus is part of a video processing data path.
3. The apparatus according to claim 1 , wherein said second byte comprises two LSBs from four pixels for 10-bit pixel data and four LSBs from two pixels for 12-bit pixel data.
4. The apparatus according to claim 1 , wherein said memory comprises a first buffer configured to store a plurality of first bytes and a second buffer configured to store a plurality of second bytes.
5. The apparatus according to claim 1 , wherein said processor comprises a direct memory access engine configured to partition said pixel data into said first byte and said second byte.
6. The apparatus according to claim 5 , wherein said direct memory access engine is further configured to reassemble said pixel data from said first byte and said second byte.
7. The apparatus according to claim 1 , wherein said processor comprises:
a compression circuit configured to generate said compressed bitstream from only the first bytes read from said memory and store said compressed bitstream in said memory; and
a decompression circuit configured to generate an 8-bit data stream in response to said compressed bitstream read from said memory.
8. The apparatus according to claim 7 , wherein said processor further comprises:
a dithering circuit configured to generate said multi-bit data stream by expanding said 8-bit data stream to said bit-depth greater than 8-bits, wherein said bit depth greater than 8-bits corresponds to a data depth of an attached display.
9. The apparatus according to claim 8 , wherein said dithering circuit is configured to generate said multi-bit data stream by adding random noise as the least significant bits of said multi-bit data stream.
10. The apparatus according to claim 1 , wherein said processor comprises:
a first DMA engine configured (i) to process the pixel data comprising eight or more bits, wherein for pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte, a number of least significant bits (LSBs) of said pixel are packed with LSBs from one or more other pixels into a second byte and (ii) to store the first byte and the second byte in the memory;
a second DMA engine configured to retrieve said first and second bytes and reassemble the pixel data having a bit-depth greater than eight bits from said first byte and said second byte;
a compression/decompression (CODEC) circuit configured (i) to generate said compressed bitstream from only the first bytes and store said compressed bitstream in the memory and (ii) to retrieve said compressed bitstream from the memory and generate an 8-bit data stream from said compressed bitstream;
a dithering circuit configured to generate said multi-bit data stream by expanding said 8-bit data stream to said bit-depth greater than eight bits; and
a display processor configured to generate said video output signal in response to (i) said original pixel data in said first mode, (ii) the reassembled pixel data in said second mode and (iii) said multi-bit data stream in said third mode.
11. The apparatus according to claim 10 , wherein said compression/decompression (CODEC) circuit comprises a video CODEC compliant with one or more compression standards selected from the group consisting of MPEG-2, MPEG-4, and H.264.
12. A video processing data path comprising:
means for processing pixel data comprising eight or more bits, wherein for pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of said pixel are packed with LSBs from one or more other pixels into a second byte;
means for storing said first byte according to a first pointer and said second byte according to a second pointer, wherein said first byte and said second byte are stored independently in a memory;
means for retrieving said first and second bytes from said memory and reassembling the pixel data having bit-depths greater than eight bits from the first and second bytes;
means for retrieving the first bytes from said memory, generating a compressed bitstream using only the first bytes, and storing said compressed bitstream in said memory, wherein said compressed bitstream comprises at least one of (i) a MPEG-2 compliant compressed bitstream, (ii) a MPEG-4 compliant compressed bitstream, and (iii) a H.264 compliant compressed bitstream;
means for retrieving said compressed bitstream from said memory and generating a multi-bit data stream having a bit-depth greater than eight bits using said compressed bitstream; and
means for generating a video output signal in response to (i) the original pixel data in a first mode, (ii) the reassembled pixel data in a second mode and (iii) the multi-bit data stream in a third mode.
13. A method for processing multi-depth video data comprising the steps of:
processing pixel data comprising eight or more bits, wherein for pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of said pixel are packed with LSBs from one or more other pixels into a second byte;
storing said first byte according to a first pointer and said second byte according to a second pointer, wherein said first byte and said second byte are stored independently in a memory;
retrieving said first and second bytes from said memory and reassembling the pixel data having bit-depths greater than eight bits from said first byte and said second byte;
retrieving only the first bytes from said memory, generating a compressed bitstream using only the first bytes and a video compressor/decompressor (CODEC), and storing said compressed bitstream in said memory, wherein said compressed bitstream comprises at least one of (i) a MPEG-2 compliant compressed bitstream, (ii) a MPEG-4 compliant compressed bitstream, and (iii) a H.264 compliant compressed bitstream;
retrieving said compressed bitstream from said memory and generating a multi-bit data stream having a bit-depth greater than eight bits using said compressed bitstream; and
generating a video output signal in response to (i) the original pixel data in a first mode, (ii) the reassembled pixel data in a second mode and (iii) the multi-bit data stream in a third mode.
14. The method according to claim 13 , wherein said second byte comprises two LSBs from four pixels for 10-bit pixel data and four LSBs from two pixels for 12-bit pixel data.
15. The method according to claim 13 , wherein said memory comprises a first buffer configured to store a plurality of first bytes and a second buffer configured to store a plurality of second bytes.
16. The method according to claim 13 , wherein the step of generating the multi-bit data stream having said bit-depth greater than eight bits comprises the steps of:
reading said compressed bitstream from said memory; and
generating an 8-bit data stream in response to said compressed bitstream.
17. The method according to claim 16 , further comprising the steps of:
generating the multi-bit data stream from said 8-bit data stream using dithering, wherein said dithering expands said 8-bit data stream to said bit-depth greater than eight bits.
18. The method according to claim 17 , wherein said dithering comprises adding random noise to the least significant bits of said multi-bit data stream.
19. The method according to claim 17 , wherein said dithering comprises adding random least significant bits to the pixel data of the 8-bit data stream.
20. The method according to claim 17 , wherein said dithering comprises performing horizontal and vertical filtering on said multi-bit data stream after adding zeroes as the least significant bits of said multi-bit data stream.