Built in self test transport controller architecture
View Patent ↗A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
1. A built in self test circuit disposed within a memory matrix, where individual memory cells within the memory matrix are disposed into logical columns, the built in self test circuit comprising:
only one memory test controller adapted to initiate test commands and receive test results, and
transport controllers, where each of the transport controllers is uniquely paired with one of the logical columns of memory cells, each of the transport controllers adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller.
2. The built in self test circuit of claim 1 , where the transport controllers are adapted to selectively operate in three different modes under control of the memory test controller, the three different modes being:
a first production testing mode for simultaneous testing of memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column,
a second production testing mode for retrieving the accumulated test results from the transport controllers, and
a diagnostic testing mode for testing memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.
3. A built in self test circuit disposed within a memory matrix, where individual memory cells within the memory matrix are disposed into logical columns, the built in self test circuit comprising:
only one memory test controller adapted to initiate test commands and receive test results, and
transport controllers, where each of the transport controllers is uniquely paired with one of the logical columns of memory cells, each of the transport controllers adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller,
where the transport controllers are adapted to selectively operate in three different modes under control of the memory test controller, the three different modes being,
a first production testing mode for simultaneous testing of memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column,
a second production testing mode for retrieving the accumulated test results from the transport controllers, and
a diagnostic testing mode for testing memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.
4. An embedded memory system, comprising:
a memory matrix, where individual memory cells within the memory matrix are disposed into logical columns,
only one memory test controller adapted to initiate test commands and receive test results, and
transport controllers, where each of the transport controllers is uniquely paired with one of the logical columns of memory cells, each of the transport controllers adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller,
where the transport controllers are adapted to selectively operate in three different modes under control of the memory test controller, the three different modes being,
a first production testing mode for simultaneous testing of memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column,
a second production testing mode for retrieving the accumulated test results from the transport controllers, and
a diagnostic testing mode for testing memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.