IP Library Patent Application 11637592
Patent Application
App. No. 11/637,592

Real time elastic FIFO latency optimization

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/637,592
Abstract

In some embodiments, a method for optimizing EFIFO latency may include one or more of the following steps: (a) counting each clock cycle from a read clock for a predetermined period of time, (b) counting each clock cycle from a write clock for a predetermined period of time, (c) comparing the counted read clock cycles to the write clock cycles to obtain a difference between the counted clock cycles, (d) adjusting a watermark for a queue based upon the difference between the counted clock cycles, (e) receiving a timeout signal, (f) terminating counting of the clock cycles of the read clock and write clock, and (g) initiating another optimization process after termination.

Claims (30)

1 . A method for optimizing EFIFO latency, comprising the steps of:

counting each clock cycle from a read clock for a predetermined period of time;

counting each clock cycle from a write clock for a predetermined period of time;

comparing the counted read clock cycles to the write clock cycles to obtain a difference between the counted clock cycles; and

adjusting a watermark for a queue based upon the difference between the counted clock cycles.

2 . The method of claim 1 , wherein the difference between the counted clock cycles is obtained by subtracting the write clock cycles from the read clock cycles.

3 . The method of claim 2 , wherein the watermark is set to a maximum value if the difference between the counted clock cycles is negative.

4 . The method of claim 2 , wherein the watermark is set to a minimum value if the difference between the counted clock cycles zero or greater.

5 . The method of claim 1 , further comprising the step of receiving a timeout signal.

6 . The method of claim 5 , further comprising terminating counting of the clock cycles of the read clock and write clock.

7 . The method of claim 6 , further comprising initiating another optimization process after termination.

8 . A optimized EFIFO system comprising:

a memory comprising:

an optimized EFIFO program that adjusts a watermark for a queue based upon a difference between read clock cycles and write clock cycles; and

a processor coupled to the memory that executes the optimized EFIFO program.

9 . The system of claim 8 , wherein the program counts read clock cycles.

10 . The system of claim 9 , wherein the program counts write clock cycles.

11 . The system of claim 10 , wherein the difference is calculated by subtracting the write clock cycles from the read clock cycles.

12 . The system of claim 11 , wherein the watermark is set to a maximum value if the difference is negative.

13 . The system of claim 12 , wherein the watermark is set to a minimum value if the difference is zero or above.

14 . A machine readable medium comprising machine executable instructions, including:

count instructions that count clock cycles from a read clock and a write clock;

compare instructions that compared the read clock cycles to the write clock cycles; and

adjust instructions that set a watermark for a queue based upon the compared value of the read clock cycles to the write clock cycles.

15 . The medium of claim 14 , wherein the compare instructions obtain the difference of the write clock cycles subtracted from the read clock cycles.

16 . The medium of claim 15 , wherein the adjust instructions set the watermark to a maximum value if the difference is a negative value.

17 . The medium of claim 16 , wherein the adjust instructions set the watermark to a minimum value if the difference is zero or greater value.

18 . The medium of claim 14 , wherein the count instructions are terminated by a timeout signal.

19 . The medium of claim 16 , wherein the maximum value is determined by the negative value.

20 . The medium of claim 18 , wherein the count instructions are initiated again after termination.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2006
From: RIDGEWAY, CURTIS A.; VISWANATH, RAVINDRA; CHEEMA, RAJINDER
To: LSI LOGIC CORPORATION
Reel/Frame 018707/0550 →