Method for request transaction ordering in OCP bus to AXI bus bridge design
View Patent ↗A request transaction ordering method and system includes designing of the Open Core Protocol (OCP) bus to an Advanced extensible Interface (AXI) bus bridge. The general flow of the bridge is to accept a plurality of read and write requests from the OCP bus and convert them to a plurality of AXI read and write requests. Control logic is set for each first in first out policy of push and pop control and for a plurality of handshake signals in OCP and in the AXI. The request ordering part of the bridge performs hazard checking to preserve required order policies for both OCP and AXI bus protocols by using a FIFO (first in first out) policy to hold the outstanding writes, a plurality of comparators, a first in first out policy to hold OCP identities for a plurality of read requests.
1. A request transaction order processing method, comprising:
applying an Open Core Protocol (OCP) to an Advanced eXtensible Interface (AXI) bus bridge for ordering request transactions in order to provide an OCP-to-AXI bridge;
accepting read and write requests from an OCP bus; and
converting said read and write requests to AXI read and write requests wherein an OCP posted write is converted to an AXI non-buffered write in order to provide enhanced request transaction ordering in a data-processing system.
2. The method of claim 1 wherein said OCP applied to said AXI bridge comprises a FIFO policy for requests.
3. The method of claim 1 wherein said OCP applied to said AXI bridge comprises an AXI write address channel, a read address channel and a write data channel output driving flip-flops.
4. The method of claim 1 wherein said OCP applied to said AXI bridge comprises a FIFO policy for writing data.
5. The method of claim 1 wherein said OCP applied to said AXI bridge comprises an AXI interface to an OCP for read response mapping logic operations.
6. The method of claim 1 further comprising a control logic circuit for controlling a plurality of FIFO policies for pushing and popping operations.
7. The method of claim 6 wherein said control logic circuit controls a plurality of handshake signals in said OCP and said AXI bridge.
8. The method of claim 1 wherein a request ordering portion of said AXI bridge uses a FIFO policy for holding an outstanding write, such that a depth of said FIFO policy is determined by a number of outstanding writes that a user desires to support.
9. The method of claim 1 wherein a request ordering portion of said AXI bridge uses a FIFO policy for holding an outstanding write, such that a width of said FIFO policy is determined by a plurality of address bits required to support a hazard checking range.
10. A request transaction order processing method, comprising:
applying an Open Core Protocol (OCP) to an Advanced eXtensible Interface (AXI) bus bridge for ordering request transactions in order to provide an OCP-to-AXI bridge, wherein said OCP applied to said AXI bridge comprises a FIFO request policy;
accepting read and write requests from an OCP bus; and
converting said read and write requests to AXI read and write requests wherein an OCP posted write is converted to an AXI non-buffered write in order to provide enhanced request transaction ordering in a data-processing system.
11. The method of claim 10 wherein said OCP applied to said AXI bridge comprises an AXI write address channel, a read address channel and a write data channel output driving flip-flops.
12. The method of claim 10 wherein said OCP applied to said AXI bridge comprises a FIFO policy for writing data.
13. A request transaction order processing system, comprising:
an Advanced eXtensible Interface (AXI) bus bridge;
an Open Core Protocol (OCP) applied to said Advanced eXtensible Interface (AXI) bus bridge in order to provide an OCP-to-AXI bridge, wherein an AXI to OCP mapping thereof allows all OCP and AXI protocols thereof to be met wherein an OCP posted write is converted to an AXI non-buffered write in order to provide enhanced request transaction ordering in a data-processing system.
14. The system of claim 13 further comprising a module for writing request information to a FIFO and control logic associated with said FIFO in order to allow an AXI wait state to be transferred back to an OCP master without losing requests.
15. The system of claim 13 further comprising a module for writing data to a FIFO and control logic associated with said FIFO in order to allow an AXI wait state to be transferred back to an OCP master without losing write data.
16. The system of claim 13 further comprising a module for implementing hazard checking of at least one read request to at least one outstanding write request via at least one comparator for writing addresses.
17. The system of claim 13 further comprising a module for driving all AXI write operations as un-buffered write operations in order to receive a response thereof for clearing a request from an outstanding write address FIFO.
18. The system of claim 13 further comprising a module for driving all AXI identification data to identical values thereof in order to prevent at least one read operation from being re-ordered and at least one write operation from being re-ordered.
19. The system of claim 13 further comprising at least one TagID FIFO for saving at least one OCP Tag ID for return to an OCP master with an associated read data and a response thereof.
20. The system of claim 13 further comprising a module for implementing hazard checking of at least one write request to at least one outstanding read request utilizing at least one comparator for reading at least one address stored in a FIFO.