Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit
View Patent ↗A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.
1. A method of avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit comprising steps of:
(a) receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer;
(b) finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information;
(c) identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer;
(d) calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire; and
(e) generating as output at least one of the wire width and the fracture interval for the dummy metal wire.
2. The method of claim 1 , the dummy metal wire in step (c) comprising multiple dummy metal wires within a selected radius from the signal wire.
3. The method of claim 2 , the selected radius being equal to a distance of one or more routing tracks.
4. The method of claim 1 , the calculated fracture interval in step (d) being equal to the maximum distance between fracture points that avoids the timing violation.
5. The method of claim 2 , the calculated fracture interval in step (d) being equal to the maximum distance between fracture points that avoids the timing violation.
6. The method of claim 1 further comprising routing the dummy metal wires at an offset spacing from the signal wires.
7. The method of claim 6 , the offset spacing being equal to half a routing track.
8. The method of claim 1 , step (d) comprising selecting the wire width of the dummy metal wire from a table of dummy metal wire widths that includes a capacitance for each dummy metal wire width.
9. The method of claim 1 , step (d) comprising selecting the fracture interval of the dummy metal wire from a table of dummy metal wire lengths that includes a capacitance for each dummy metal wire length.
10. A computer readable storage medium tangibly embodying instructions that when executed by a computer implement a method for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit, the method comprising steps of:
(a) receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer;
(b) finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information;
(c) identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer;
(d) calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire; and
(e) generating as output at least one of the wire width and the fracture interval for the dummy metal wire.
11. The computer readable storage medium of claim 10 , the dummy metal wire in step (c) comprising multiple dummy metal wires within a selected radius from the signal wire.
12. The computer readable storage medium of claim 11 , the selected radius being equal to a distance of one or more routing tracks.
13. The computer readable storage medium of claim 10 , the calculated fracture interval in step (d) being equal to the maximum distance between fracture points that avoids the timing violation.
14. The computer readable storage medium of claim 11 , the calculated fracture interval in step (d) being equal to the maximum distance between fracture points that avoids the timing violation.
15. The computer readable storage medium of claim 10 further comprising routing the dummy metal wires at an offset spacing from the signal wires.
16. The computer readable storage medium of claim 15 , the offset spacing being equal to half a routing track.
17. The computer readable storage medium of claim 10 , step (d) comprising selecting the wire width of the dummy metal wire from a table of dummy metal wire widths that includes a capacitance for each dummy metal wire width.
18. The computer readable storage medium of claim 10 , step (d) comprising selecting the fracture interval of the dummy metal wire from a table of dummy metal wire lengths that includes a capacitance for each dummy metal wire length.