IP Library Granted Patent US 7,463,267
Granted Patent B2
US 7,463,267 · App. 11/588,087 · Granted Dec 9, 2008

System for interleaved storage of video data

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Quick Facts
Patent No.
US 7,463,267
App. No.
11/588,087
Granted
Dec 9, 2008
Kind
B2
Abstract

A method for reading atoms positioned within a memory having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) designating a first atom within the strip, (d) locating one or more second atoms to be paired with the first atom, (e) determining whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (f) reading the legitimate pair from the first memory portion and the second memory portion.

Claims (49)

1. A method for reading atoms positioned within a memory having a first memory portion and a second memory portion, comprising the steps of:

(A) positioning said atoms across said memory;

(B) defining a strip across a portion of said atoms, wherein said strip comprises a rectangular arrangement of said atoms stored in said first and second memory by (i) alternating each atom between said first and second memory in a horizontal direction and (ii) alternating every two of said atoms between said first and second memory in a vertical direction;

(C) designating a first atom within said strip;

(D) locating a second atom to be paired with said first atom;

(E) determining whether said second atom when paired with said first atom forms a legitimate pair, wherein said legitimate pair occurs when (i) said first atom is positioned in said first memory portion and said second atom is positioned in said second memory portion and (ii) said first and second atom are read during a common clock cycle;

(F) reading said legitimate pair from said first memory portion and said second memory portion on said common clock cycle; and

(G) repeating steps (C)-(F) until all of said atoms of said strip are read.

2. The method according to claim 1 , wherein step (a) further comprises the step of:

positioning said atoms into said first memory portion and said second memory portion.

3. The method according to claim 1 , wherein said first memory portion comprises a first dynamic random access memory and said second memory portion comprises a second dynamic random access memory.

4. The method according to claim 1 , wherein step (c) further comprises the step of: designating said first atom as the top left atom positioned within said strip.

5. The method according to claim 1 , wherein step (d) further comprises the step of:

designating an atom immediately to the right of said first atom to be said second atom.

6. The method according to claim 5 , further comprising the step of:

designating an atom immediately below said first atom to be said second atom.

7. The method according to claim 6 , further comprising the step of:

designating an atom two scan lines vertically below said first atom in said strip to be said second atom for a frame access.

8. The method according to claim 6 , further comprising the step of:

designating an atom two scan lines vertically below said first atom in said strip to be said second atom for a field access.

9. The method according to claim 1 , wherein

said first memory portion comprises a left dynamic random access memory and said second memory portion comprises a right dynamic access memory.

10. The method according to claim 1 , wherein step (e) further comprises the step of:

determining that said second atom forms said legitimate pair with said first atom when the pair formed between said first atom and said second atom does not cross a horizontal tile boundary.

11. The method according to claim 1 , wherein step (e) further comprises the step of:

determining that said second atom forms said legitimate pair with said first atom when said first atom and said second atom have not been read from said memory.

12. The method according to claim 1 , further comprising the step of:

supplying bank and column addresses to said first memory portion and said second memory portion.

13. The method according to claim 1 , wherein step (B) further comprises the step of:

defining said strip across an even or odd number of said atoms.

14. The method according to claim 1 , wherein said atom comprises a minimum addressable unit of data.

15. The method according to claim 1 , wherein step (F) further comprises the step of:

reading said legitimate pair from said first memory and said second memory in a raster scan order.

16. The method according to claim 3 , further comprising the step of:

supplying bank and column addresses to said first dynamic random access memory and said second dynamic random access memory, wherein said first dynamic random access memory is addressed independently from said second dynamic access memory.

17. The method according to claim 1 , wherein step (F) further comprises the step of:

transferring one or more legitimate pairs into a barrel shifter.

18. The method according to claim 17 , further comprising the step of:

transferring said one or more legitimate pairs into said barrel shifter in a raster scan order.

19. The method according to claim 1 , wherein step (D) further comprises the step of:

storing said second atom in a temporary register when said second atom is read out of order prior to performing step (E).

20. An apparatus comprising:

means for positioning atoms across a memory having a first memory portion and a second memory portion;

means for defining a strip across a portion of said atoms, wherein said strip comprises a rectangular arrangement of said atoms stored in said first and second memory by (i) alternating each atom between said first and second memory in a horizontal direction and (ii) alternating every two of said atoms between said first and second memory in a vertical direction;

means for designating a first atom within said strip;

means for locating a second atom to be paired with said first atom;

means for determining whether said second atom when paired with said first atom forms a legitimate pair, wherein said legitimate pair occurs when (i) said first atom is positioned in said first memory portion and said second atom is positioned in said second memory portion and (ii) said first and second atom are read during a common clock cycle;

means for reading said legitimate pair from said first memory portion and said second memory portion; and

means for repeating steps (C)-(F) until all of said atoms of said strip are read.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2007
From: WISE, ADRIAN PHILIP; DARNES, JAMES A.
To: LSI LOGIC CORPORATION
Reel/Frame 019141/0345 →