IP Library Granted Patent US 7,397,401
Granted Patent B2
US 7,397,401 · App. 11/483,056 · Granted Jul 8, 2008

Arithmetic decode without renormalization costs

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Quick Facts
Patent No.
US 7,397,401
App. No.
11/483,056
Granted
Jul 8, 2008
Kind
B2
Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.

Claims (31)

1. An apparatus comprising:

a first circuit configured to generate context information in response to one or more bins on a binary signal; and

a second circuit configured to generate said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein said second circuit is further configured to (i) perform said renormalization once per bin and (ii) read a predetermined number of said input bits while performing said renormalization once per bin.

2. The apparatus according to claim 1 , wherein said second circuit comprises a renormalization circuit configured to (i) perform said renormalization and (ii) read said predetermined number of input bits on said bitstream signal.

3. The apparatus according to claim 2 , wherein said second circuit comprises an arithmetic decoder circuit configured to calculate and present a range value to said renormalization circuit.

4. The apparatus according to claim 3 , wherein said renormalization circuit is configured to compare said range value to a predetermined range value.

5. The apparatus according to claim 4 , wherein said renormalization circuit is configured to multiply said range value with a first value to produce an update range value if said range value is less than said predetermined range value.

6. The apparatus according to claim 4 , wherein said renormalization circuit presents said updated range value to said arithmetic decoder circuit until said updated range value is greater than or equal to a predetermined range value.

7. The apparatus according to claim 5 , wherein said renormalization circuit is configured to multiply an offset value with a second value to produce a multiplied offset value.

8. The apparatus according to claim 3 , wherein said range value indicates the number of iterations needed to perform renormalization on said context information.

9. The apparatus according to claim 1 , wherein said apparatus is implemented as a context adaptive binary arithmetic-coding decoder.

10. The apparatus according to claim 2 , wherein said renormalization circuit further comprises:

one or more barrel shifters configured to perform shift operations; and

a priority encoder configured to determine the number of shift operations to be performed by said one or more barrel shifters.

11. An apparatus comprising:

means for generating context information in response to one or more bins on a binary signal; and

means for generating said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein said means for generating said binary signal is further configured to (i) perform said renormalization once per bin and (ii) read a predetermined number of said input bits while performing said renormalization once per bin.

12. A method for context adaptive binary arithmetic decoding comprising the steps of:

(a) generating context information in response to one or more bins on a binary signal; and

(b) generating said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein step (b) includes the sub-steps of (i) performing said renormalization once per bin and (ii) reading a predetermined number of said input bits while performing said renormalization once per bin.

13. The method according to claim 12 , further comprising the step of:

calculating a range value.

14. The method according to claim 13 , further comprising the step of:

comparing said range value to a predetermined range value.

15. The method according to claim 14 , further comprising the step of:

multiplying said range value with a first value to produce an update range value if said range value is less than said predetermined range value.

16. The method according to claim 15 , further comprising the step of:

presenting said updated range value until said updated range value is greater than or equal to a predetermined range value.

17. The method according to claim 16 , further comprising the step of:

multiplying an offset value with a second value to produce a multiplied offset value.

18. The method according to claim 13 , wherein said range value indicates the number of iterations needed to perform renormalization on said context information.

Assignments (10)
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To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
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To: LSI CORPORATION; AGERE SYSTEMS LLC
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
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CHANGE OF NAME Recorded Jun 6, 2014
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From: BANWAIT, HARMINDER S.; PEARSON, ERIC C.; JAMES, SCOTT F.
To: LSI LOGIC CORPORATION
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