Efficient 8×8 CABAC residual block transcode system
A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 4×4 CAVLC residual blocks. The second module configured to generate a plurality of scanning position signals based on the metric signals. The third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling the parsed residual blocks based on the scanning position signals.
1. A circuit comprising:
a first module configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from said parsing of said 4×4 CAVLC residual blocks;
a second module configured to generate a plurality of scanning position signals based on said metric signals; and
a third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling said parsed residual blocks based on said scanning position signals.
2. The circuit according to claim 1 , wherein said third module comprises a fourth module configured to generate an array of significant coefficient flags during said parsing of a trailing ones syntax and a coefficient level syntax element of said input signal.
3. The circuit according to claim 2 , wherein said first module is further configured to receive a value in said input signal of a number of zero-valued transform coefficient levels located before a position of a last non-zero transform coefficient level.
4. The circuit according to claim 3 , wherein said third module further comprises a fifth module configured to reorder said array where said value is greater than zero.
5. The circuit according to claim 4 , wherein said array is reordered during said parsing of a run_before syntax element of said input signal.
6. The circuit according to claim 4 , wherein said third module further comprises a sixth module configured to reorder said parsed residual blocks where said value is greater than zero.
7. The circuit according to claim 6 , wherein said parsed residual blocks are reordered during said parsing of a run_before syntax element of said input signal.
8. The circuit according to claim 6 , wherein said third module is further configured to generate said output signal based on said array and said parsed residual blocks where said value is zero.
9. The circuit according to claim 6 , wherein said third module is further configured to generate said output signal based on said array as reordered and said parsed residual blocks as reordered where said value is greater than zero.
10. The circuit according to claim 1 , further comprising an arithmetic encoder configured to generate a bitstream by encoding said output signal, wherein said bitstream is compliant with an H.264 recommendation High 10 profile.
11. A method for 8×8 context-based adaptive binary arithmetic coding (CABAC) residual block transcoding, comprising the steps of:
(A) generating a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal;
(B) generating a plurality of metric signals resulting from said parsing of said 4×4 CAVLC residual blocks;
(C) generating a plurality of scanning position signals based on said metric signals; and
(D) generating an 8×8 CABAC residual block in an output signal by up-sampling said parsed residual blocks based on said scanning position signals.
12. The method according to claim 11 , wherein step (D) comprises the sub-step of:
generating an array of significant coefficient flags during said parsing of a trailing ones syntax element and a coefficient level syntax element of said input signal.
13. The method according to claim 12 , further comprising the step of:
receiving a value in said input signal of a number of zero-valued transform coefficient levels located before a position of a last non-zero transform coefficient level.
14. The method according to claim 13 , further comprising the step of:
reordering said array where said value is greater than zero.
15. The method according to claim 14 , wherein said array is reordered during said parsing of a run_before syntax element of said input signal.
16. The method according to claim 14 , further comprising the step of:
reordering said parsed residual blocks where said value is greater than zero.
17. The method according to claim 16 , wherein said parsed residual blocks are reordered during said parsing of a run_before syntax element of said input signal.
18. The method according to claim 16 , wherein step (D) comprises the sub-step of:
generating said output signal based on said array and said parsed residual blocks where said value is zero.
19. The method according to claim 16 , wherein step (D) comprises the sub-step of:
generating said output signal based on said array as reordered and said parsed residual blocks as reordered where said value is greater than zero.
20. A device comprising:
means for generating a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal;
means for generating a plurality of metric signals resulting from said parsing of said 4×4 CAVLC residual blocks;
means for generating a plurality of scanning position signals based on said metric signals; and
means for generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling said parsed residual blocks based on said scanning position signals.