IP Library Granted Patent US 6,918,026
Granted Patent B2
US 6,918,026 · App. 09/821,893 · Granted Jul 12, 2005

External device transmission system and a fast pattern processor employing the same

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Quick Facts
Patent No.
US 6,918,026
App. No.
09/821,893
Granted
Jul 12, 2005
Kind
B2
Abstract

For use with a fast pattern processor having an internal function bus, an external device transmission system, method for transmitting commands to an external device, and a fast pattern processor employing the system and method. In one embodiment, the external device transmission system includes a context memory subsystem that maintains a plurality of argument signature registers, each of the plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument. The external device transmission system also includes a pattern processing engine that dynamically modifies an argument and generates a transmit command as a function of a context associated with the modified argument. The external device transmission system still further includes an output interface subsystem that receives the transmit command, and transmits the modified argument based upon the transmit command to an external device.

Claims (43)

1. For use with a fast pattern processor having an internal function bus, an external device transmission system, comprising:

a context memory subsystem configured to maintain a plurality of argument signature registers, each of said plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument;

a pattern processing engine configured to dynamically modify an argument and generate a transmit command as a function of a context associated with said modified argument; and

an output interface subsystem configured to receive said transmit command, and transmit said modified argument based upon said transmit command to an external device.

2. The external device transmission system as recited in claim 1 wherein said modified argument contains data selected from the group consisting of:

an external device command,

a routing parameter, and

a protocol data unit classification.

3. The external device transmission system as recited in claim 1 wherein said pattern processing engine is further configured to generate said transmit command based on said external device.

4. The external device transmission system as recited in claim 1 wherein said output interface subsystem is further configured to transmit portions of a protocol data unit and said modified argument to said external device.

5. The external device transmission system as recited in claim 1 wherein said external device is a routing switch processor.

6. The external device transmission system as recited in claim 1 wherein said pattern processing engine is further configured to dynamically modify said modified argument based upon a content of a protocol data unit.

7. The external device transmission system as recited in claim 1 wherein said pattern processing engine is configured to employ a sequence of operating instructions defined by a functional programing language.

8. For use with a fast pattern processor having an internal function bus, a method for transmitting commands to an external device, comprising:

maintaining a plurality of argument signature registers, each of said plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument;

dynamically modifying an argument;

generating a transmit command as a function of a context associated with said modified argument; and

transmitting said modified argument based upon said transmit command to an external device.

9. The method as recited in claim 8 wherein said modified argument contains data selected from the group consisting of:

an external device command,

a routing parameter, and

a protocol data unit classification.

10. The method as recited in claim 8 wherein said generating said transmit command is further based on said external device.

11. The method as recited in claim 8 wherein said transmitting further comprises transmitting portions of a protocol data unit and said modified argument to said external device.

12. The method as recited in claim 8 wherein said external device is a routing switch processor.

13. The method as recited in claim 8 wherein said dynamically modifying further comprises dynamically modifying said modified argument based upon a content of a protocol data unit.

14. The method as recited in claim 8 wherein said dynamically modifying employs a sequence of operating instructions defined by a functional programing language.

15. A fast pattern processor, comprising:

an internal function bus;

an external device transmission system, including:

a context memory subsystem that maintains a plurality of argument signature registers, each of said plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument,

a pattern processing engine that dynamically modifies an argument and generates a transmit command as a function of a context associated with said modified argument, and

an output interface subsystem that receives said transmit command, and transmits said modified argument based upon said transmit command to an external device; and

a data buffer controller that stores configuration information into a portion of said context memory subsystem associated with said corresponding context.

16. The fast pattern processor as recited in claim 15 wherein said modified argument contains data selected from the group consisting of:

an external device command,

a routing parameter, and

a protocol data unit classification.

17. The fast pattern processor as recited in claim 15 wherein said pattern processing engine is further configured to generate said transmit command based on said external device.

18. The fast pattern processor as recited in claim 15 wherein said output interface subsystem further transmits portions of a protocol data unit and said modified argument to said external device.

19. The fast pattern processor as recited in claim 15 wherein said external device is a routing switch processor.

20. The fast pattern processor as recited in claim 15 wherein said pattern processing engine further dynamically modifies said modified argument based upon a content of a protocol data unit.

21. The fast pattern processor as recited in claim 15 wherein said pattern processing engine employs a sequence of operating instructions defined by a functional programing language.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
CERTIFICATE OF CONVERSION Recorded Oct 19, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034014/0846 →
MERGER Recorded Oct 19, 2014
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 033977/0311 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →