IP Library Granted Patent US 9,148,520
Granted Patent B2
US 9,148,520 · App. 14/136,203 · Granted Sep 29, 2015

Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,148,520
App. No.
14/136,203
Granted
Sep 29, 2015
Kind
B2
Abstract

An apparatus comprising a decision circuit, a detector circuit and a processing circuit. The decision circuit may be configured to generate a confirmation signal in response to a first lock signal and a second lock signal. The detector circuit may be configured to generate the first lock signal in response to a filtered version of an input signal being above a threshold. The processing circuit may be configured to generate the second lock signal in response to a power signal received from the detector circuit. The processing circuit generates the second lock signal by analyzing the rising edge of a frequency power envelope of the power signal.

Claims (20)

1. An apparatus comprising:

a decision circuit configured to generate a confirmation signal in response to a first lock signal and a second lock signal;

a detector circuit configured to generate said first lock signal in response to a filtered version of an input signal being above a threshold; and

a processing circuit configured to generate said second lock signal in response to a power signal received from said detector circuit, wherein said processing circuit generates said second lock signal by analyzing a rising edge of a frequency power envelope of said power signal.

2. The apparatus according to claim 1 , wherein said processing circuit analyzes two consecutive frequency power estimation windows.

3. The apparatus according to claim 1 , wherein said processing circuit analyzes three or more consecutive frequency power estimation windows when the input signal is noisy.

4. The apparatus according to claim 1 , wherein said confirmation signal confirms said input signal is a signaling tone.

5. The apparatus according to claim 1 , wherein said processing circuit stores a history of rising edge parameters of said power signal in a buffer.

6. The apparatus according to claim 5 , wherein said history is used to generate said second lock signal.

7. The apparatus according to claim 6 , wherein said second lock signal is generated by calculating a difference between a current power signal to a previous power signal.

8. The apparatus according to claim 1 , wherein said detector circuit generates an average power signal to compare to said threshold.

9. The apparatus according to claim 1 , wherein said processing circuit generates said second lock signal in further response to analyzing amplitude fluctuations and frequency instability of said power signal.

10. A method for detecting tone, comprising the steps of:

(A) generating a confirmation signal in response to a first lock signal and a second lock signal;

(B) generating said first lock signal in response to a filtered version of an input signal being above a threshold; and

(C) generating said second lock signal in response to a power signal, wherein said method generates said second lock signal by analyzing a rising edge of a frequency power envelope of said power signal.

11. An apparatus comprising:

means for generating a confirmation signal in response to a first lock signal and a second lock signal;

means for generating said first lock signal in response to a filtered version of an input signal being above a threshold; and

means for generating said second lock signal in response to a power signal, wherein said apparatus generates said second lock signal by analyzing a rising edge of a frequency power envelope of said power signal.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2013
From: DZIK, DARIUSZ; BARAZESH, BAHMAN
To: LSI CORPORATION
Reel/Frame 031828/0624 →