IP Library Granted Patent US 8,499,137
Granted Patent B2
US 8,499,137 · App. 12/963,895 · Granted Jul 30, 2013

Memory manager for a network communications processor architecture

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Quick Facts
Patent No.
US 8,499,137
App. No.
12/963,895
Granted
Jul 30, 2013
Kind
B2
Abstract

Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.

Claims (52)

1. A memory manager for a network processor having a plurality of processing modules, the memory manager coupled to at least one shared memory, the memory manager comprising:

a memory manager core configured to allocate one or more blocks of the at least one shared memory to a requesting one of the plurality of processing modules;

a free block list configured to track availability of one or more memory blocks of the shared memory;

a reference counter configured to maintain, for each allocated memory block, a reference count value indicating a number of access requests of corresponding ones of the plurality of processing modules accessing the memory block, the reference count value located with data at the allocated memory block;

a memory access accumulator configured to, for one or more subsequent access requests to a given memory address corresponding to an allocated memory block concurrent with processing of at least one prior access request to the given memory address: (i) accumulate an incremental value corresponding to the one or more subsequent access requests, (ii) update the reference count value associated with the given memory address, and (iii) update a value stored at the given memory address with the accumulated incremental value during a data operation corresponding to a most recent of the one or more subsequent access requests.

2. The memory manager of claim 1 , wherein the reference counter maintains the reference count value of a given allocated memory block by incrementing the reference count value for each corresponding processing module accessing the given allocated memory block, and decrementing the reference count value when a corresponding processing module ends accessing the memory block.

3. The memory manager of claim 2 , wherein, when a number of free memory blocks in the free block list reaches a minimum threshold, the memory manager core is further configured to deny a memory allocation request of the requesting one of the plurality of processing modules.

4. The memory manager of claim 1 , wherein a size for each memory block is selected as one of: 256 B, 2 kB, 16 kB, and 64 kB.

5. The memory manager of claim 1 , wherein each memory block includes a corresponding reserved area for protection data.

6. The memory manager of claim 5 , wherein the protection data includes at least one of: (i) parity data of the data stored in the corresponding memory block; (ii) error correction code (ECC) data of the data stored in the corresponding memory block; and (iii) a unique identifier of a corresponding processing module of the network processor associated with the corresponding allocated memory block.

7. The memory manager of claim 6 , wherein:

the protection data is 32 bits long and is split into four 8 bit sections;

the corresponding reserved area is 128 bits long; and

the four 8 bit sections of the protection data are padded with a fixed pattern of data corresponding to the processing module of the network processor to which the corresponding memory block is allocated, wherein the fixed pattern of data is 96 bits long and is split into four 24 bit sections.

8. The memory manager of claim 1 , wherein the network processor is implemented in an integrated circuit.

9. A method of managing a shared memory of a network processor having a plurality of processing modules and at least one shared memory, the method comprising:

allocating, by a memory manager core, one or more blocks of the at least one shared memory to a requesting one of the plurality of processing modules;

tracking, by a free block list, availability of one or more memory blocks of the shared memory;

maintaining, by a reference counter, for each allocated memory block, a reference count value indicating a number of access requests of corresponding ones of the plurality of processing modules accessing the memory block, the reference count value located with data at the allocated memory block;

for one or more subsequent access requests to a given memory address corresponding to an allocated memory block concurrent with processing of at least one prior access request to the given memory address:

accumulating, by a memory access accumulator, an incremental value corresponding to the one or more subsequent access requests;

updating the reference count value associated with the given memory address; and

updating a value stored at the given memory address with the accumulated incremental value during a data operation corresponding to a most recent of the one or more subsequent access requests.

10. The method of claim 9 , further comprising:

incrementing, by the reference counter, the reference count value of a given allocated memory block for each corresponding processing module accessing the given allocated memory block; and

decrementing, by the reference counter, the reference count value when a corresponding processing module ends accessing the memory block.

11. The method of claim 10 , further comprising:

denying, by the memory manager core, when a number of free memory blocks in the free block list reaches a minimum threshold, a memory allocation request of the requesting one of the plurality of processing modules.

12. The method of claim 9 , wherein a size for each memory block is selected as one of: 256 B, 2 kB, 16 kB, and 64 kB.

13. The method of claim 9 , further comprising:

generating, by the memory manager core, for each of the plurality of processing modules of the network processor, a unique identifier corresponding to each processing module;

writing protection data to a corresponding reserved area of an allocated memory block, wherein the protection data includes the unique identifier of a corresponding one of the processing modules to which the corresponding memory block is allocated.

14. The method of claim 13 , wherein the protection data includes at least one of: (i) parity data of the data stored in the corresponding memory block; (ii) error correction code (ECC) data of the data stored in the corresponding memory block; and (iii) a unique identifier of a corresponding processing module of the network processor associated with the corresponding allocated memory block.

15. The method of claim 14 , wherein the protection data is 32 bits long and is split into four 8 bit sections and the corresponding reserved area is 128 bits long, and wherein the method further comprises:

padding, by the memory manager core, the four 8 bit sections of the protection data with the unique identifier corresponding to the processing module to which the corresponding memory block is allocated, wherein the unique identifier is 96 bits long and is split into four 24 bit sections.

16. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of managing a shared memory of a network processor having a plurality of processing modules and at least one shared memory, the method comprising:

allocating, by a memory manager core, one or more blocks of the at least one shared memory to a requesting one of the plurality of processing modules;

tracking, by a free block list, availability of one or more memory blocks of the shared memory;

maintaining, by a reference counter, for each allocated memory block, a reference count value indicating a number of access requests of corresponding ones of the plurality of processing modules accessing the memory block, the reference count value located with data at the allocated memory block;

for one or more subsequent access requests to a given memory address corresponding to an allocated memory block concurrent with processing of at least one prior access request to the given memory address:

accumulating, by a memory access accumulator, an incremental value corresponding to the one or more subsequent access requests;

updating the reference count value associated with the given memory address; and

updating a value stored at the given memory address with the accumulated incremental value during a data operation corresponding to a most recent of the one or more subsequent access requests.

17. The non-transitory machine-readable storage medium of claim 16 , further comprising:

incrementing, by the reference counter, the reference count value of a given allocated memory block for each corresponding processing module accessing the given allocated memory block; and

decrementing, by the reference counter, the reference count value when a corresponding processing module ends accessing the memory block.

18. The non-transitory machine-readable storage medium of claim 17 , further comprising:

denying, by the memory manager core, when a number of free memory blocks in the free block list reaches a minimum threshold, a memory allocation request of the requesting one of the plurality of processing modules.

19. The non-transitory machine-readable storage medium of claim 16 , wherein a size for each memory block is selected as one of: 256 B, 2 kB, 16 kB, and 64 kB.

20. The non-transitory machine-readable storage medium of claim 16 , further comprising:

generating, by the memory manager core, for each of the plurality of processing modules of the network processor, a unique identifier corresponding to each processing module;

writing protection data to a corresponding reserved area of an allocated memory block, wherein the protection data includes the unique identifier of a corresponding one of the processing modules to which the corresponding memory block is allocated.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2010
From: HASTING, JOSEPH; MITAL, DEEPAK
To: LSI CORPORATION
Reel/Frame 025488/0338 →