IP Library Granted Patent US 9,727,508
Granted Patent B2
US 9,727,508 · App. 13/705,822 · Granted Aug 8, 2017

Address learning and aging for network bridging in a network processor

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Quick Facts
Patent No.
US 9,727,508
App. No.
13/705,822
Granted
Aug 8, 2017
Kind
B2
Abstract

Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Claims (94)

1. A method of processing data packets received by a network processor comprising a plurality of processing modules and at least one shared memory, the method comprising:

receiving a data packet by the network processor, the data packet including an associated source address and at least one associated destination address;

determining, by an I/O adapter of the network processor, whether the at least one associated destination address is stored in a memory of the I/O adapter;

if the at least one associated destination address is stored in the I/O adapter memory:

processing the received data packet in accordance with one or more bridging rules associated with each destination address stored in the I/O adapter memory;

if the at least one associated destination address is not stored in the I/O adapter memory:

sending, by the I/O adapter, a task message via a task communication ring bus of the network processor, to a processing module of the network processor, the task message comprising the at least one associated destination address;

determining, by the processing module, whether the at least one associated destination address in the task message is stored in an address table stored in the at least one shared memory of the network processor;

if the at least one associated destination address is stored in the address table:

processing, based on the task message, the received data packet in accordance with one or more bridging rules associated with each destination address stored in the address table; and

updating, based on the bridging rules associated with the destination address stored in the address table, the bridging rules associated with the destination address stored in the I/O adapter memory,

wherein the I/O adapter memory has lower access latency than the address table.

2. The method of claim 1 , wherein the source address and the destination address each comprise one or more of a media access control (MAC) address and a port identifier.

3. The method of claim 1 , further comprising:

if the at least one associated destination address is not stored in either the I/O adapter memory or the address table, broadcasting, by the network processor, a packet to all destinations coupled to the network processor, the packet requesting that a network device corresponding to the destination address send a response packet to the network processor.

4. The method of claim 1 , further comprising:

determining whether the associated source address of the received data packet is stored in the I/O adapter memory;

if the associated source address is not stored in the I/O adapter memory:

updating the bridging rules associated with the source address stored in the I/O adapter memory;

sending, by the I/O adapter, a task message to a processing module of the network processor, the task message comprising the associated source address;

processing, by the processing module of the network processor based on the task message, the received data packet in accordance with the updated bridging rules associated with the associated source address; and

updating, based on the updated bridging rules associated with the source address stored in the I/O adapter memory, the bridging rules associated with the source address stored in the address table.

5. The method of claim 4 , further comprising:

if the associated source address is stored in the I/O adapter memory:

determining whether the port identifier associated with the source address of the received data packet matches the port identifier associated with the source address in the I/O adapter memory by the steps of:

updating, by the I/O adapter, aging data corresponding to the source address stored in the I/O adapter memory;

sending, by the I/O adapter, a task message to a processing module of the network processor, the task message comprising the updated aging data corresponding to the source address; and

updating, by the processing module based on the task message, the aging data associated with the source address stored in the address table.

6. The method of claim 5 , wherein:

if the port identifier for the associated source address of the received data packet does not match the port identifier for the source address stored in the I/O adapter memory:

updating the port identifier for the source address stored in the I/O adapter memory;

sending a task message to a processing module of the network processor, the task message comprising the updated port identifier for the source address; and

updating, by the processing module based on the task message, the port identifier associated with the source address stored in the address table.

7. The method of claim 1 , further comprising:

if the I/O adapter memory has reached a filled threshold when a data packet having a new address is received:

selecting an entry of the I/O adapter memory to be overwritten by the new address;

updating the entry of the I/O adapter memory with the new address;

starting an aging timer for the updated entry of the I/O adapter memory;

sending a task message to a processing module of the network processor, the task message comprising the updated address;

updating, by the processing module, the address table; and

starting an aging timer for the updated address in the address table.

8. The method of claim 7 , wherein the step of selecting an existing stored address in the I/O adapter memory to be overwritten by the new address comprises:

selecting a relative oldest entry stored in the I/O adapter memory.

9. The method of claim 1 , further comprising:

when the address table has reached a filled threshold:

maintaining synchronization between the I/O adapter memory and the address table by not storing new addresses in the I/O adapter memory.

10. The method of claim 1 , the I/O adapter comprising a timer corresponding to each entry in the I/O adapter memory, the method further comprising:

starting a timer corresponding to an entry of the I/O adapter memory when an address is stored in the memory entry;

resetting and restarting the timer corresponding to a memory entry when a subsequent packet is received having an address matching the address stored in the memory entry if the subsequent packet is received before the timer reaches a threshold;

if the timer reaches a threshold:

removing the stored address from the I/O adapter memory; and

sending a task message to a processing module of the network processor indicating the removal of the stored address from the I/O adapter memory.

11. The method of claim 1 , wherein the method is implemented by a machine executing program code encoded on a non-transitory machine-readable storage medium.

12. A network processor for processing data packets received from a communication link coupled to a packet-switched network, the network processor comprising:

a plurality of processing modules and at least one shared memory;

an I/O adapter configured to determine (i) an associated source address of each received data packet and at least one associated destination address of each received data packet, and (ii) whether the at least one associated destination address is stored in a memory of the I/O adapter;

if the at least one associated destination address is stored in the I/O adapter memory, the I/O adapter is configured to:

process the received data packet in accordance with one or more bridging rules associated with each destination address stored in the I/O adapter memory;

if the at least one associated destination address is not stored in the I/O adapter memory, the I/O adapter is configured to:

send a task message via a task communication ring bus of the network processor to one of the plurality of processing modules of the network processor, the task message comprising the at least one associated destination address, wherein the processing module is configured to determine whether the at least one associated destination address in the task message is stored in an address table stored in the at least one shared memory;

if the at least one associated destination address is stored in the address table, the processing module is configured to:

process, based on the task message, the received data packet in accordance with one or more bridging rules associated with each destination address stored in the address table; and

update, based on the bridging rules associated with the destination address stored in the address table, the bridging rules associated with the destination address stored in the I/O adapter memory,

wherein the I/O adapter memory has lower access latency than the address table.

13. The network processor of claim 12 , wherein the source address and the destination address each comprise one or more of a media access control (MAC) address and a port identifier.

14. The network processor of claim 12 , wherein, if the at least one associated destination address is not stored in either the I/O adapter memory or the address table, the network processor is configured to broadcast a packet to all destinations coupled to the network processor, the packet requesting that a network device corresponding to the destination address send a response packet to the network processor.

15. The network processor of claim 12 , wherein:

the I/O adapter is further configured to:

determine whether the associated source address of the received data packet is stored in the I/O adapter memory;

if the associated source address is not stored in the I/O adapter memory:

update the bridging rules associated with the source address stored in the I/O adapter memory; and

send a task message to one of the processing modules of the network processor, the task message comprising the associated source address, wherein the processing module is configured to (i) process, based on the task message, the received data packet in accordance with the updated bridging rules associated with the associated source address, and (ii) update, based on the updated bridging rules associated with the source address stored in the I/O adapter memory, the bridging rules associated with the source address stored in the address table.

16. The network processor of claim 15 , wherein, if the associated source address is stored in the I/O adapter memory:

the I/O adapter is further configured to:

determine whether the port identifier associated with the source address of the received data packet matches the port identifier associated with the source address in the I/O adapter memory;

update aging data corresponding to the source address stored in the I/O adapter memory; and

send a task message to a processing module of the network processor, the task message comprising the updated aging data corresponding to the source address, wherein the processing module is configured to, based on the task message, update the aging data associated with the source address stored in the address table.

17. The network processor of claim 16 , wherein, if the port identifier for the associated source address of the received data packet does not match the port identifier for the source address stored in the I/O adapter memory:

the I/O adapter is further configured to:

update the port identifier for the source address stored in the I/O adapter memory; and

send a task message to a processing module of the network processor, the task message comprising the updated port identifier for the source address, wherein the processing module is configured to, based on the task message, update the port identifier associated with the source address stored in the address table.

18. The network processor of claim 12 , wherein, if the I/O adapter memory has reached a filled threshold when a data packet having a new address is received:

the I/O adapter is further configured to:

select an entry of the I/O adapter memory to be overwritten by the new address;

update the entry of the I/O adapter memory with the new address;

start an aging timer for the updated entry of the I/O adapter memory;

send a task message to a processing module of the network processor, the task message comprising the updated address, wherein the processing module is configured to (i) update the address table, and (ii) start an aging timer for the updated address in the address table.

19. The network processor of claim 12 , wherein, when the address table has reached a filled threshold, the I/O adapter is configured to maintain synchronization between the I/O adapter memory and the address table by not storing new addresses in the I/O adapter memory.

20. The network processor of claim 12 , wherein the I/O adapter comprises a timer corresponding to each entry in the I/O adapter memory, and the I/O adapter is further configured to:

start a timer corresponding to an entry of the I/O adapter memory when an address is stored in the memory entry;

reset and restart the timer corresponding to a memory entry when a subsequent packet is received having an address matching the address stored in the memory entry if the subsequent packet is received before the timer reaches a threshold;

if the timer reaches a threshold:

remove the stored address from the I/O adapter memory; and

send a task message to a processing module of the network processor indicating the removal of the stored address from the I/O adapter memory.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2012
From: MUNOZ, ROBERT J.; MANZELLA, JOSEPH A.; GUO, ZHONG; ROPER, WALTER A.
To: LSI CORPORATION
Reel/Frame 029411/0586 →