Virtual concatenation of PDH signals
View Patent ↗Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The extracted delays enables the receiver to realign the various frames of the PDH signal to reconstitute the originally transmitted signals that travel through different paths of the transport network linking the source and sink of the virtually concatenated channel.
1. A method for transmitting data over a plurality of channels each associated with a PDH signal said plurality of channels to be virtually concatenated to form a single second channel larger than each of the plurality of channels, the method comprising:
encapsulating the data packets;
inverse multiplexing said encapsulated data packets into N PDH signals, each PDH signal comprising P frames; wherein N and P are non-zero integers;
forming M groups of overhead bits for each of the N PDH signals, each of the M groups of overhead bits comprising a sequence number indicator and a multi-frame indicator;
substituting a different one of the M groups of overhead bits for a corresponding number of payload bits in one frame or a subframe out of every P frames of an associated PDH signal thereby to form M×P frames wherein M is a non-zero integer; and
transmitting each of the M×P frames, wherein × represents a multiplication operation, wherein each of the transmitted M groups of overhead bits forms an overhead packet that enables a receiver to determine the status of the M×P frames and extract the differential delay experienced by the N PDH signals as they are routed through the virtually concatenated channels.
2. The method of claim 1 wherein said PDH signal is selected from a group consisting of DS1, DS3, E1 and E3 signals.
3. The method of claim 1 wherein said encapsulation further comprises Generic Framing Procedure encapsulation.
4. The method of claim 1 wherein said PDH signal is a DS1 signal and said M is 16, wherein each of the 16 groups of overhead bits comprises an octet disposed adjacent the framing bit of a first frame of the 24 multi-frames of the DS1 signal.
5. The method of claim 1 wherein said PDH signal is an E1 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the time slot zero of a first frame of the 16 multi-frames of the E1 signal.
6. The method of claim 1 wherein said PDH signal is a DS3 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the X1 bit of a first frame of the 7 multi-frames of the DS3 signal.
7. The method of claim 1 wherein said PDH signal is an E3 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the second frame alignment byte of the E3 multi-frame.
8. The method of claim 1 wherein said M is 16 and wherein said 16 groups of overhead bits comprise Link Capacity Adjustment Scheme (LCAS) bits and virtual concatenation (VCAT) bits.
9. The method of claim 1 wherein said PDH signal is a DS1 signal and said M is 8, wherein each of the 8 groups of overhead bits comprises an octet disposed adjacent the framing bit of a first frame of the 24 multi-frames of the DS1 signal.
10. The method of claim 1 wherein said PDH signal is an E1 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the time slot zero of a first frame of the 16 multi-frames of the E1 signal.
11. The method of claim 1 wherein said PDH signal is a DS3 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the X1 bit of a first frame of the 7 multi-frames of the DS3 signal.
12. The method of claim 1 wherein said PDH signal is an E3 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the second frame alignment byte of the E3 multi-frame.
13. The method of claim 1 further comprising:
receiving the P×M frames;
extracting differential delay information from the received overhead bits of the P×M frames; and
extracting status information from the received overhead bits of the P×M frames.
14. An apparatus configured to transmit data over a plurality of channels each associated with a plesiochronous digital hierarchy (PDH) signal, said plurality of channels to be virtually concatenated to form a single second channel larger than each of the plurality of channels the apparatus comprising:
an encapsulation module configured to encapsulate the data packets;
an inverse multiplexer configured to inverse multiplex said encapsulated data packets into N PDH signals, each PDH signal comprising P frames; wherein N and P are non-zero integers;
an overhead processor configured to:
form M groups of overhead bits for each of the N PDH signals, each of the M groups of overhead bits comprising a sequence number indicator and a multi-frame indicator; and
substitute a different one of the M groups of overhead bits for a corresponding number of payload bits in one frame or a subframe out of every P frames of an associated PDH signal thereby to form M×P frames; wherein M is a non-zero integer; and
a transmitter configured to transmit each of the M×P frames, wherein × represents a multiplication operation, wherein each of the transmitted M groups of overhead bits forms an overhead packet that enables a receiver to determine the status of the M×P frames and extract the differential delay experienced by the N PDH signals as they are routed through the virtually concatenated channels.
15. The apparatus of claim 14 wherein said PDH signal is selected from a group consisting of DS1, DS3, E1 and E3 signals.
16. The apparatus of claim 14 wherein said encapsulation module is further configured to encapsulated in accordance with Generic Framing Procedure encapsulation.
17. The apparatus of claim 14 wherein PDH signal is a DS1 signal and said M is 16, wherein each of the 16 groups of overhead bits comprises an octet disposed adjacent the framing bit of a first frame of the 24 multi-frames of the DS1 signal.
18. The apparatus of claim 14 wherein said PDH signal is an E1 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the time slot zero of a first frame of the 16 multi-frames of the E1 signal.
19. The apparatus of claim 14 wherein said PDH signal is a DS3 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the X1 bit of a first frame of the 7 multi-frames of the DS3 signal.
20. The apparatus of claim 14 wherein said PDH signal is an E3 signal and said M is 16, wherein each of the 16 groups of the overhead bits comprises an octet disposed adjacent the second frame alignment byte of the E3 multi-frame.
21. The apparatus of claim 14 wherein said M is 16 and wherein said 16 groups of overhead bits comprise Link Capacity Adjustment Scheme (LCAS) bits and virtual concatenation (VCAT) bits.
22. The apparatus of claim 14 wherein said PDH signal is a DS1 signal and said M is 8, wherein each of the 8 groups of overhead bits comprises an octet disposed adjacent the framing bit of a first frame of the 24 multi-frames of the DS1 signal.
23. The apparatus of claim 14 wherein said PDH signal is an E1 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the time slot zero of a first frame of the 16 multi-frames of the DS3 signal.
24. The apparatus of claim 14 wherein said PDH signal is a DS3 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the X1 bit of a first frame of the 7 multi-frames of the DS3 signal.
25. The apparatus of claim 14 wherein said PDH signal is an E3 signal and said M is 8, wherein each of the 8 groups of the overhead bits comprises an octet disposed adjacent the second frame alignment byte of the E3 multi-frame.
26. The apparatus of claim 14 further comprising:
a receiver configured to receive the transmitted P×M frames;
a second overhead processor configured to extract differential delay information from the received overhead bits of the P×M frames, and further to extract status information from the received overhead bits of the P×M frames.