Patent Assignment
Reel/Frame 037675/0129
Release of Security Interest
Recorded: 2016-02-01
Pages: 72
Assignor
BANK OF AMERICA, N.A.
Executed: 2016-01-15
Assignees
PMC-SIERRA, INC.
3975 FREEDOM CIRCLE, SUITE 100, SANTA CLARA, CALIFORNIA, 95054
PMC-SIERRA US, INC.
3975 FREEDOM CIRCLE, SUITE 100, SANTA CLARA, CALIFORNIA, 95054
WINTEGRA, INC.
3975 FREEDOM CIRCLE, SUITE 100, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(690)
Prefetch/Prestore Mechanism for Peripheral Controllers with Shared Internal Bus
Patent:
5,557,750 →
Application:
07/963,583 →
Scsi Host Adapter with Shared Command and Data Buffer
Patent:
5,732,223 →
Application:
07/963,584 →
A Progammably Configurable Host Adapter Integrated Circuit Including a Risc Processor
Patent:
5,659,690 →
Application:
07/964,532 →
Interface and Control Circuit for Regulating Data Flow in a Scsi Initiator with Multiple Host Bus Interface Selection
Patent:
5,544,326 →
Application:
08/029,910 →
Software Configurable Isa Bus Card Interface with Security Access Read and Write Sequence to Upper Data Bits at Addresses Used by a Game Device
Patent:
5,522,086 →
Application:
08/143,363 →
System for Starting and Completing a Data Transfer for a Subsequently Received Autotransfer Command After Receiving a First Scsi Data Transfer Command That Is Not Autotransfer
Patent:
5,634,081 →
Application:
08/205,002 →
Scsi Command Descriptor Block Parsing State Machine
Patent:
5,504,868 →
Application:
08/205,003 →
Scsi Host Adapter Integrated Circuit Utilizing a Sequencer Circuit to Control at Least One Non-Data Scsi Phase Without Use of Any Processor
Patent:
5,655,147 →
Application:
08/229,864 →
Dynamic Power Saving Video Dac
Patent:
5,489,902 →
Application:
08/233,928 →
Atm Switching Element and Method Having Independently Accessible Cell Memories
Patent:
5,583,861 →
Application:
08/235,006 →
All Mos Voltage to Current Converter
Patent:
5,550,495 →
Application:
08/241,720 →
Efficient Data Storage Arrangement for Far-End Echo Canceller
Patent:
5,473,600 →
Application:
08/246,722 →
Integrated User Network Interface Device
Patent:
5,568,486 →
Application:
08/250,895 →
Pair Division Multiplexer for Digital Communications
Patent:
5,461,621 →
Application:
08/251,958 →
High-Speed Cmos Pseudo-Ecl Output Driver
Patent:
5,548,230 →
Application:
08/251,960 →
Method for Protecting an Asic by Resetting It After a Predetermined Time Period
Patent:
5,537,055 →
Application:
08/269,083 →
Method for Accessing a Sequencer Control Block by a Host Adapter Integrated Circuit
Patent:
5,564,023 →
Application:
08/269,463 →
Global Parity Symbol for Interleaved Reed-Solomon Coded Data
Patent:
5,642,366 →
Application:
08/270,858 →
Pro-Capture Circuit for Phase Locked Loop Circuits
Patent:
5,436,597 →
Application:
08/272,837 →
Error Free Data Transfers
Patent:
5,598,552 →
Application:
08/285,755 →
Status Indicator for a Host Adapter
Patent:
5,657,455 →
Application:
08/301,458 →
A Universal Programming Interface for Clock Generators Operable in a Parallel Programming Mode and a Serial Programming Mode
Patent:
5,586,309 →
Application:
08/341,036 →
Method and Apparatus for Recovering a Variable Bit Rate Service Clock
Patent:
5,548,580 →
Application:
08/350,550 →
Clock Recovery Phase Locked Loop Control Using Clock Difference Detection and Forced Low Frequency Startup
Patent:
5,512,860 →
Application:
08/352,744 →
Error Generation Circuit for Testing a Digital Bus
Patent:
5,701,409 →
Application:
08/392,442 →
Methods and Apparatus for Enqueueing Data Cells in an Atm Switch Fabric Architecture
Patent:
5,570,348 →
Application:
08/439,078 →
Methods and Apparatus for Enqueueing and Dequeueing Data Cells in an Atm Switch Fabric Architecture
Patent:
5,557,607 →
Application:
08/439,147 →
Programmable Jump Window for Sonet Compliant Bit Error Monitoring
Patent:
5,606,563 →
Application:
08/444,307 →
Approach for Identifying a Subset of Asynchronous Transfer Mode (Atm) Vpi/Vci Values in the Complete Vpi/Vci Range
Patent:
5,815,737 →
Application:
08/461,450 →
System for Generating Second Interrupt Signal for Data Transfer Completion for a First Scsi Data Transfer Command That Is Not Autotransfer
Patent:
5,640,593 →
Application:
08/462,719 →
System for Supplying Initiator Identification Information to Scsi Bus in a Reselection Phase of an Initiator Before Completion of an Autotransfer Command
Patent:
5,845,154 →
Application:
08/463,333 →
Method for Receiving a First Scsi Command, Subsequent Receiving Second Scsi Command and Starting Data Transfer, Reconnecting and Performing Data Transfer for First Scsi Command
Patent:
5,752,083 →
Application:
08/463,617 →
Method of Flagging the Completion of a Second Command Before the Completion of a First Command from the Same Initiator in a Scsi Controller
Patent:
5,603,066 →
Application:
08/463,649 →
System for Storing Initiator, Queue Tag and Logical Block Information, Disconnecting from Target If Command Is Not Auto Transfer, Reconnecting and Performing Data Transfer
Patent:
5,781,803 →
Application:
08/465,075 →
Integrated Circuit with a Serial Port Having Only One Pin
Patent:
5,826,068 →
Application:
08/482,529 →
A Deskew Circuit in a Host Interface Circuit
Patent:
5,748,806 →
Application:
08/486,084 →
A Method of Operation of a Host Adapter Integrated Circuit
Patent:
5,838,950 →
Application:
08/486,096 →
Method and Apparatus for Implementing an Application Programming Interface for a Communications Bus
Patent:
5,815,678 →
Application:
08/503,078 →
Approach to Directly Performing Asynchronous Transfer Mode (Atm) Adaptation Layer 5 Reassembly
Patent:
5,642,347 →
Application:
08/516,215 →
Preserving Configuration Information in a Scam Based Scsi System
Patent:
5,692,134 →
Application:
08/532,919 →
State Machine Architecture for Concurrent Processing of Multiplexed Data Streams
Patent:
5,640,398 →
Application:
08/551,530 →
Split Video Architecture for Personal Computers
Patent:
5,808,630 →
Application:
08/552,771 →
Allowed Cell Rate Reciprocal Approximation in Rate-Based Available Bit Rate Schedulers
Patent:
5,751,697 →
Application:
08/568,347 →
Traffic Controller for Cell-Based Transmission
Patent:
5,668,797 →
Application:
08/568,379 →
Ring Oscillator Having a Substantially Sinusoidal Signal
Patent:
5,677,650 →
Application:
08/574,922 →
Cmos Sonet/Atm Receiver Suitable for Use with Pseudo Ecl and Ttl Signaling Enviroments
Patent:
5,793,225 →
Application:
08/581,901 →
Single Pin Crystal Oscillator Circuit
Patent:
5,675,294 →
Application:
08/582,881 →
A Serial Port Having Only a Single Terminal for Information Transfer to and from an Integrated Circuit
Patent:
5,920,708 →
Application:
08/592,800 →
Method for Specifying Concurrent Execution of a String of I/O Command Blocks in a Chain Structure
Patent:
5,850,567 →
Application:
08/615,476 →
Host Adapter System Including an Integrated Pci Buffer Controller and Xor Function Circuit
Patent:
5,881,250 →
Application:
08/615,477 →
Hardware Method for Verifying That an Area of Memory Has Only Zero Values
Patent:
5,867,732 →
Application:
08/615,478 →
Method for Concurrently Executing a Configured String of Concurrent I/O Command Blocks Within a Chain Concurrently to Perform a Raid 5 I/O Operation
Patent:
5,892,969 →
Application:
08/615,479 →
Power Supply Self-Adjusted Circuit for Dual or Multiple Voltage Integrated Circuits
Patent:
5,825,166 →
Application:
08/615,883 →
Chain Manager for Use in Executing a Chain of I/O Command Blocks
Patent:
5,768,621 →
Application:
08/616,817 →
Method for Specifying Execution of Only One of a Pair of I/O Command Blocks in a Chain Structure
Patent:
5,797,034 →
Application:
08/616,836 →
Method for Enhancing Performance of a Raid 1 Read Operation Using a Pair of I/O Command Blocks in a Chain Structure
Patent:
5,758,187 →
Application:
08/616,838 →
I/O Command Block Chain Structure in a Memory
Patent:
5,812,877 →
Application:
08/616,846 →
Asynchronous Bit-Table Calendar for Atm Switch
Patent:
5,844,901 →
Application:
08/616,875 →
Method for Sequencing Execution of I/O Command Blocks in a Chain Structure by Setting Hold-Off Flags and Configuring a Counter in Each I/O Command Block
Patent:
5,923,896 →
Application:
08/617,990 →
A Method of Enabling and Disabling a Data Function in an Integrated Circuit
Patent:
5,991,861 →
Application:
08/617,991 →
Available Bit Rate Scheduler
Patent:
5,706,288 →
Application:
08/622,398 →
Method and Apparatus for Recovery of Peak Cell Rate Tokens in an Atm Network Interface
Patent:
5,771,228 →
Application:
08/648,710 →
Low Voltage Silicon Cotrolled Rectifier Structure for Esd Input Pad Protection in Cmos Ic's
Patent:
5,734,541 →
Application:
08/650,836 →
Process Compensated Integrated Circuit Output Driver
Patent:
5,760,618 →
Application:
08/664,119 →
Variable Bit Rate Scheduler
Patent:
5,745,490 →
Application:
08/666,087 →
Combination Local Atm Segmentation and Reassembly and Physical Layer Device
Patent:
5,742,765 →
Application:
08/666,088 →
Atm Architecture and Switching Element
Patent:
6,151,301 →
Application:
08/680,869 →
Global Parity Symbol for Interleaved Reed-Solomon Coded Data
Patent:
5,872,799 →
Application:
08/687,009 →
Error Generation Circuit for Testing a Digital Bus
Patent:
5,978,934 →
Application:
08/797,802 →
Interleaved Burst Xor Using a Single Memory Pointer
Patent:
5,946,707 →
Application:
08/808,526 →
Shift Register-Based Xor Accumulator Engine for Generating Parity in a Data Processing System
Patent:
5,896,406 →
Application:
08/829,044 →
Write Synchronization System on a Headerless Format Magnetic Disk Device
Patent:
6,084,739 →
Application:
08/829,432 →
Methods and Apparatuses for Automatic Bank Switching in a Host Adapter Memory
Patent:
6,003,017 →
Application:
08/866,427 →
External I/O Controller System for an Independent Access Parity Disk Array
Patent:
6,012,123 →
Application:
08/872,019 →
Programmable Logic Datapath That May Be Used in a Field Programmable Device
Patent:
6,006,321 →
Application:
08/874,817 →
Status Indicator for a Host Adapter
Patent:
5,978,863 →
Application:
08/876,539 →
Full Enclosure Chassis System with Tool-Free Access to Hot-Pluggable Circuit Boards Therein
Patent:
6,061,250 →
Application:
08/882,170 →
High-Speed Serial Data Cable with Improved Electromagnetic Performance
Patent:
6,109,971 →
Application:
08/887,349 →
Command Interpreter System in an I/O Controller
Patent:
5,931,920 →
Application:
08/906,369 →
System for Copying Iobs from Fifo into I/O Adapter, Writing Data Completed Iob, and Invalidating Completed Iob in Fifo for Reuse of Fifo
Patent:
5,905,905 →
Application:
08/906,765 →
Method of Forming a High-Precision Linear Mos Capaciotr Using Conventional Mos Device Processing Steps
Patent:
6,063,659 →
Application:
08/923,810 →
Method and Apparatus for Determining Sector Addresses from Media Having Data Written in a Headerless Format
Patent:
6,023,387 →
Application:
08/926,303 →
Method and Apparatus to Identify Flows in Data Systems
Patent:
6,275,861 →
Application:
08/937,285 →
Apparatus and Method for Communication Between Integrated Circuits Connected to Each Other by a Single Line
Patent:
6,393,576 →
Application:
08/938,828 →
Three-State Phase-Dectector/Charge Pump Iwth No Dead-Band Offering Tunable Phase in Phase-Locked Circuits
Patent:
5,917,352 →
Application:
08/941,347 →
Integrated Pci Buffer Controller and Xor Function Circuit
Patent:
5,974,530 →
Application:
08/942,373 →
Reconfigurable Arithmetic Datapath
Patent:
5,974,435 →
Application:
08/953,766 →
Datapath Control Logic for Processors Having Instruction Set Architectures Implemented with Hierarchically Organized Primitive Operations
Patent:
6,016,539 →
Application:
08/963,345 →
Adaptable Input/Output Pin Control
Patent:
5,923,894 →
Application:
08/963,346 →
Processor Having an Instruction Set Architecture Implemented with Hierarchically Organized Primitive Operations
Patent:
5,940,626 →
Application:
08/963,387 →
Virtual Register Sets
Patent:
6,178,482 →
Application:
08/963,391 →
System and Method for Real-Time Data Backup Using Snapshot Copying with Selective Campaction of Backup Data
Patent:
6,061,770 →
Application:
08/963,754 →
File Array Communications Interface for Communicating Between a Host Computer and an Adapter
Patent:
6,009,478 →
Application:
08/963,902 →
File Array Storage Architecture Having File System Distributed Across a Data Processing Platform
Patent:
6,219,693 →
Application:
08/964,304 →
Mechanism to Support an Utopia Interface Over a Backplane
Patent:
6,147,997 →
Application:
08/965,737 →
Many Dimensional Congestion Detection System and Method
Patent:
6,134,218 →
Application:
08/970,882 →
Command Queuing System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,088,740 →
Application:
08/988,016 →
Method and Apparatus for High-Speed, Scalable Communication System
Patent:
6,188,690 →
Application:
08/988,940 →
Decentralized File Mapping in a Striped Network File System in a Distributed Computing Environment
Patent:
6,029,168 →
Application:
09/012,267 →
Method for Selectively Booting from a Desired Peripheral Device
Patent:
6,105,130 →
Application:
09/016,764 →
Method and System for Managing Storage Devices Over a Network
Data Transfer Between Small Computer System Interface Systems
Patent:
6,021,454 →
Application:
09/049,522 →
Serial/Parallel Ghz Transceiver with Pseudo-Random Built in Self Test Pattern Generator
Patent:
6,201,829 →
Application:
09/055,197 →
Fault Tolerant Redundant Bus Bridge Systems and Methods
Patent:
6,202,115 →
Application:
09/062,279 →
Redundant Bus Bridge Systems and Methods Using Selectively Synchronized Clock Singals
Patent:
5,991,844 →
Application:
09/062,282 →
Method and Apparatus for Detecting Disabled Physical Devices and Deleting Undeliverable Cells
Patent:
6,226,298 →
Application:
09/067,705 →
Bus Termination Circuitry and Methods for Implementing the Same
Patent:
6,122,689 →
Application:
09/078,346 →
Scatter Gather Memory System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,105,075 →
Application:
09/083,569 →
Scsi Bus Transceiver and Method for Making the Same
Patent:
6,173,344 →
Application:
09/085,671 →
Source-Destination Re-Timed Cooperative Communication Bus
Patent:
6,157,971 →
Application:
09/088,812 →
Host Adapter Having a Snapshot Mechanism
Patent:
6,298,403 →
Application:
09/089,030 →
System for Data Stream Packer and Unpacker Integrated Circuit Which Align Data Stored in a Two Level Latch
Patent:
6,065,066 →
Application:
09/089,039 →
Multiple Access Memory Architecture
Patent:
6,240,482 →
Application:
09/089,044 →
Decoupled Serial Memory Access with Passkey Protected Memory Areas
Patent:
6,148,384 →
Application:
09/089,057 →
Host Adapter Capable of Simultaneously Transmitting and Receiving Data of Multiple Contexts Between a Computer Bus and Peripheral Bus
Patent:
6,202,105 →
Application:
09/089,274 →
A Host Adapter Having Paged Data Buffers for Continuously Transferring Data Between a System Bus and a Peripheral Bus
Patent:
6,070,200 →
Application:
09/089,311 →
Broadcast Command Packet Protocol for Scsi Interface
Patent:
6,477,165 →
Application:
09/097,899 →
Quick Arbitration and Select (Qas) Protocol in Scsi Interface for Configuring a Current Target Device to Assert a Qas Message Code During a Message-in Phase
Patent:
6,058,436 →
Application:
09/098,214 →
Digital Control of a Linc Linear Power Amplifier
Patent:
6,054,894 →
Application:
09/100,568 →
Methods of and Apparatus for Monitoring the Termination Status of a Scsi Bus
Patent:
6,154,067 →
Application:
09/130,196 →
Data Alignment System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,145,017 →
Application:
09/130,322 →
Bbs One Bios Image Multicard Support
Patent:
6,061,745 →
Application:
09/133,736 →
Asynchronous Bit-Table Calendar for Atm Switch
Patent:
6,430,186 →
Application:
09/134,635 →
Method and Apparatus of Boot Device Switching by a Floppy Disk
Patent:
6,158,002 →
Application:
09/134,760 →
Intelligent Input/Output Target Device Communication and Exception Handling
Patent:
6,182,182 →
Application:
09/181,712 →
Fibre Channel Controller Having Both Inbound and Outbound Control Units for Simultaneously Processing Both Mutiple Inbound and Outbound Sequences
Patent:
6,425,034 →
Application:
09/183,164 →
Fibre Channel Loop Map Initialization Protocol Implemented in Hardware
Patent:
6,470,026 →
Application:
09/183,580 →
Method for Reassembling Data Frames Received-Out of Order with Respect to a Data Sequence Using Expected Frame Information and Buffer List Calculations
Patent:
6,314,477 →
Application:
09/183,865 →
Command Forwarding: a Method for Optimizing I/O Latency and Throughput in Fibre Channel Client/Server/Target Mass Storage Architectures
Patent:
6,493,750 →
Application:
09/183,969 →
Transmission of Fcp Response in the Same Loop Tenancy as the Fcp Data with Minimization of Inter-Sequence Gap
Patent:
6,463,498 →
Application:
09/183,970 →
Data Fault Tolerance Software Apparatus and Method
Patent:
6,427,212 →
Application:
09/191,943 →
Method and Apparatus for Performing Internet Network Address Translation
Patent:
6,457,061 →
Application:
09/199,839 →
Method for Specifying Concurrent Execution of a String of I/O Command Blocks in a Chain Structure
Patent:
6,157,964 →
Application:
09/205,142 →
Controller and Associated Methods for a Linc Linear Power Amplifier
Patent:
6,054,896 →
Application:
09/216,067 →
Compensation System and Methods for a Linear Power Amplifier
Patent:
5,990,738 →
Application:
09/216,091 →
System and Methods for Stimulating and Training a Linc Power Amplifier During Non-Transmission Events
Patent:
5,990,734 →
Application:
09/216,092 →
Method and Apparatus for High-Speed Network Rule Processing
Patent:
7,136,926 →
Application:
09/224,382 →
Method and Apparatus for High-Speed Network Rule Processing
Patent:
6,691,168 →
Application:
09/246,572 →
Raid Architecture with Two-Drive Fault Tolerance
Patent:
6,353,895 →
Application:
09/250,657 →
Error Generation Circuit for Testing a Digital Bus
Patent:
6,049,894 →
Application:
09/255,406 →
Computer System Storage
Patent:
6,922,688 →
Application:
09/261,708 →
Automatic Multi-Mode Termination
Patent:
6,378,025 →
Application:
09/273,401 →
Storage Area Network Administration
Patent:
7,107,534 →
Application:
09/275,727 →
Method and Apparatus for High-Speed Network Rule Processing
Patent:
6,510,509 →
Application:
09/280,235 →
Method and Apparatus for Creating Formatted Fat Partitions with a Hard Drive Having a Bios-Less Controller
Patent:
6,192,456 →
Application:
09/281,715 →
Universal Option Rom Bios Including Multiple Option Bios Images for Multichip Support and Boot Sequence for Use Therewith
Patent:
6,425,079 →
Application:
09/282,919 →
System for Efficient Broadband Data Payload Conversion
Patent:
6,603,776 →
Application:
09/286,211 →
Ultra Thin and Flexible Scsi Cable and Method for Making the Same
Patent:
6,124,551 →
Application:
09/299,688 →
Method and Apparatus for Efficient Selection of a Boundary Value
Patent:
6,341,296 →
Application:
09/300,357 →
Method and System for Automatically Determining Maxiumum Data Throughput Over a Bus
Patent:
6,442,628 →
Application:
09/300,818 →
Packet-Switch System
Patent:
6,647,019 →
Application:
09/303,765 →
Control System for High Speed Rule Processors
Patent:
6,611,875 →
Application:
09/305,783 →
Interface Between a Link Layer Device and One or More Physical Layer Devices
Patent:
6,850,523 →
Application:
09/313,267 →
Fast Stack Save and Restore System and Method
Patent:
6,449,709 →
Application:
09/321,329 →
Method for Flashing a Read Only Memory (Rom) Chip of a Host Adapter with Updated Option Rom Bios Code
Patent:
6,282,647 →
Application:
09/324,347 →
Multiple Chip Single Image Bios
Patent:
6,446,139 →
Application:
09/340,539 →
A Scsi Phase Status Register for Use in Reducing Instructions Executed by an on-Chip Sequencer in Asserting a Scsi Ackowledge Signal and Method
Programmable Logic Datapath That May Be Used in a Field Programmable Device
Patent:
6,121,791 →
Application:
09/343,389 →
Hardware Attention Management Circuit and Method for Parallel Scsi Host Adapters
Patent:
6,415,347 →
Application:
09/344,291 →
Programmable Logic Datapath
Patent:
6,150,836 →
Application:
09/346,556 →
Egress Port Scheduling Using Memory Efficient Request Storage
Patent:
6,463,484 →
Application:
09/350,166 →
Topology-Independent Priority Arbitration for Stackable Frame Switches
Patent:
6,467,006 →
Application:
09/350,738 →
Link Aggregation in Ethernet Frame Switches
Patent:
6,553,029 →
Application:
09/351,406 →
Dual-Drive Fault Tolerant Method and System for Assigning Data Chunks to Column Parity Sets
Patent:
6,453,428 →
Application:
09/354,426 →
Data, Path and Flow Integrity Monitor
Patent:
6,490,317 →
Application:
09/374,995 →
Self-Healing Computer System Storage
Patent:
6,449,731 →
Application:
09/375,909 →
Object Oriented Fault Tolerance
Patent:
6,742,137 →
Application:
09/376,773 →
Host-Memory Based Raid System, Device, and Method
Patent:
6,526,477 →
Application:
09/389,954 →
Sums of Production Datapath
Patent:
6,438,569 →
Application:
09/399,981 →
Self-Healing Computer System Storage
Patent:
6,530,036 →
Application:
09/439,440 →
Method and System for Negotiation of the Highest Common Link Rate Among Nodes of a Fibre Channel Arbitrated Loop
Patent:
6,477,171 →
Application:
09/452,618 →
Method of Conserving Memory Resources by Directly Decompressing a Compressed Bios Associated with an Option Rom Bios Chip to an Allocated Conventional Memory of System Memory
Patent:
6,567,911 →
Application:
09/455,301 →
Pos-Phy Interface for Interconnection of Physical Layer Devices and Link Layer Devices
Patent:
6,668,297 →
Application:
09/459,972 →
System and Method for Parity Caching Based on Stripe Locking in Raid Data Storage
Patent:
6,542,960 →
Application:
09/464,127 →
System and Method for Data Storage Archive Bit Update After Snapshot Backup
Patent:
6,460,054 →
Application:
09/464,250 →
System and Method for Accomplishing Data Storage Migration Between Raid Levels
Patent:
6,510,491 →
Application:
09/465,057 →
F5-To-F4 Oam Alarm Notification and Cell Generation in Multiple Connection Atm Switches
Patent:
6,865,183 →
Application:
09/465,339 →
Scaleable Bandwidth Interconnect for Simultaneous Transfer of Mixed Pleisiochronous Digital Hierarcy (Pdh) Clients
Patent:
6,584,521 →
Application:
09/472,153 →
Fibre Channel Interface Controller That Performs Non-Blocking Output and Input of Fibre Channel Data Frames and Acknowledgement Frames to and from a Fibre Channel
Patent:
6,791,989 →
Application:
09/474,945 →
Count/Address Generation Circuitry
Patent:
6,601,158 →
Application:
09/475,647 →
Method and System for Efficient I/O Operation Completion in a Fibre Channel Node
Patent:
6,578,096 →
Application:
09/475,907 →
Method and System for Efficient I/O Operation Completion in a Fibre Channel Node Using an Application Specific Integration Circuit and Determining I/O Operation Completion Status Within an Interface Controller
Patent:
6,526,458 →
Application:
09/475,908 →
Digital Delay Line with Synchronous Control
Page Memory Management in Non Time Critical Data Buffering Applications
Patent:
6,366,996 →
Application:
09/489,917 →
Method and System Increasing Performance Substituting Finite State Machine Control with Hardware-Implemented Data Structure Manipulation
Patent:
6,978,457 →
Application:
09/494,817 →
Use of Antiphase Signals for Predistortion Training Within an Amplifier System
Patent:
6,313,703 →
Application:
09/517,702 →
Mos Varactor Structure with Engineered Voltage Control Range
Patent:
6,407,412 →
Application:
09/523,592 →
Host adapter having paged payload buffers for simultaneously transferring data between a computer bus and a peripheral bus
Patent:
6,279,051 →
Application:
09/531,869 →
Method and Apparatus for Programmable Lexical Packet Classifier
Patent:
7,185,081 →
Application:
09/538,132 →
High-speed, adaptive IDDQ measurement
Patent:
6,342,790 →
Application:
09/548,745 →
Short and Long Term Fair Shuffling for Crossbar Switch Arbiter
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6,735,212 →
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Input/Output Communication Networks and Booting Protocols
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6,691,160 →
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Method and Apparatus for Grammatical Packet Classifier
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Intelligent Expansion Rom Sharing Bus Subsystem
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Parallel String Pattern Searches in Respective Ones of Array of Nanocomputers
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Method and Apparatus for Interconnection of Flow-Controlled Communication
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Serial port for a hose adapter integrated circuit using a single terminal
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Serial Bus for Connecting Two Integrated Circuits with Storage for Input / Output Signals
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Method and Apparatus for Managing Data Traffic Between a High Capacity Source and Multiple Destinations
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Two-Dimensional Execution Queue for Host Adapters
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Digital Predistortion Methods for Wideband Amplifiers
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Wideband Digital Predistortion Linearizer for Nonlinear Amplifiers
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Transmission Antenna Array System with Predistortion
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Amplifier measurement and modeling processes for use in generating predistortion parameters
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Predistortion amplifier system with separately controllable amplifiers
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System and Method for Detecting of Unchanged Parity Data
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System and Method for Zeroing Data Storage Blocks in a Raid Storage Implementation
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System and Method for Detection of Disk Storage Blocks Containing Unique Values
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Bus Interface for Cell and/or Packet Data Transfer
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Programmable logic datapath that may be used in a field programmable device
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Methods for Associating End Nodes on a Fabric
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Forward Performance Monitoring Cell Generation in Atm Oam Processing
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Low charge-injection charge pump
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Switched Capacitor Transmitter Pre-Driver
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Jitter Frequency Shifting Delta-Sigma Modulated Signal Synchronization Mapper
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Contention-Based Methods for Generating Reduced Number of Interrupts
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File array storage architecture having file system distributed across a data processing platform
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Dual-Channel Scsi Chips and Methods for Configuring Separate Interoperability of Each Channel of the Scsi Chip
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Method and Apparatus for Establishing a Profile Table for Host Bus Adapters
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Method and Apparatus for a Layer Structure Directory for Common Hardware Interface Modules
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Method and Apparatus for Device Discovery
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Method and Apparatus for Address Mapping
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Controller Fault Recovery System for a Distributed File System
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Adaptive Phase Shift Filtration of Pointer Justification Jitter in Synchronous-Plesiosynchronous Signal Desynchronization
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Method for Signaling in a High Speed Communication System
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Method and Apparatus for High-Speed Communication System
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Apparatus for a Switch Element in a High Speed Communication System
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Method of for manipulating cells in a high speed communication system
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Method and System for Flow Control During the Data Out Phase of the Packetized Scsi Protocol
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Method and Structure for Supporting Flow Control by a Scsi Initiator During the Data Out Phase of the Packetized Scsi Protocol
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Method and Structure for Supporting Flow Control by a Scsi Target During the Data Out Phase of the Packetized Scsi Protocol
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Method and Structure for Supporting Data Streaming by a Scsi Initiator During the Data in Phase of the Packetized Scsi Protocol
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System Interface for Cell and/or Packet Transfer
Advanced Adaptive Pre-Distortion in a Radio Frequency Transmitter
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Bipartite Graphical Connection Scheduling in Time and Space Switch Fabrics
Method and Apparatus for Intelligent Failover in a Multi-Path System
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Intelligent Load Balancing for a Multi-Path Storage System
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Low Noise Wideband Digital Predistortion Amplifier
Wideband Analog Quadrature Modulator/Demodulator with Pre-Compensation/Post-Compensation Correction
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Multi-Channel Clock Recovery Circuit
Crossbar Subsystem and Method
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Multicast Cell Scheduling Protocol
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Apparatus and Method for Determining Byte Gain and Loss Adjustments in a Sonet/Sdh Network Element
I/O Subsystem Topology Discovery Method
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Automatic Addressing of Expanders in I/O Subsystem
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Multi-Channel Sonet/Sdh Desynchronizer
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Method and System for Error Correction Over Serial Link
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09/846,875 →
Expander Device for Isolating Bus Segments in I/O Subsystem
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09/846,975 →
Network Switch Port with Weighted Random Early Discard
Network Switch Port Traffic Manager Having Configurable Packet and Cell Servicing
Fair Weighted Queuing Bandwidth Allocation System for Network Switch Port
Back Pressure Control System for Network Switch Port
Multiservice Switching System with Distributed Switch Fabric
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Flexible Fifo System for Interfacing Between Datapaths of Variable Length
Expander Device and Method for Resetting Bus Segments in I/O Subsystem Segmented with Expanders
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Method and Apparatus for Scheduling Static and Dynamic Traffic Through a Switch Fabric
Method and Apparatus for Scalable Error Correction Code Generation Performance
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Application:
09/872,830 →
Sparse Byte Enable Indicator for High Speed Memory Access Arbitration Method and Apparatus
Method and Apparatus for Post Boot-Up Domain Validation
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Amplifier Measurement and Modeling Processes for Use in Generating Predistortion Parameters
Amplifier Measurement and Modeling Processes for Use in Generating Predistortion Parameters
Method and Apparatus for Improved Raid 1 Write Performance in Low Cost Systems
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Traffic Manager for Network Switch Port
Buffer Manager for Network Switch Port
Systems and Methods for the Dynamic Range Compression of Multi-Bearer Single-Carrier and Multi-Carrier Waveforms
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Methods for Optimizing Memory Resources During Initialization Routines of a Computer System
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Application:
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Structure and Method for Linking Scatter/Gather List Segments for Host Adapters
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Application:
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Transmit Virtual Concatenation Processor
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Methods and Systems to Transfer Information Using an Alternative Routing Associated with a Communication Network
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Mask-Based Round Robin Arbitration
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Method and Management Port for an Indirect Loop Protocol Associated with an Interconnect Device
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Method and System for Configuring an Interconnect Device
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Application:
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Method and System to Manage Resource Requests Utilizing Link-List Queues Within an Arbiter Associated with an Interconnect Device
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Multicast Cell Buffer for Network Switch
Method and Apparatus for a Virtual Memory File System
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Method and Apparatus for Extending Storage Functionality at the Bios Level
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Method and System to Allocate Resources Within an Interconnect Device According to a Resource Allocation Table
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Apparatus and Methodology for an Input Port of a Switch That Supports Cut-Through Operation Within the Switch
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Method and System to Map a Service Level Associated with a Packet to One of a Number of Data Streams at an Interconnect Device
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A Congestion Management in a Distributed Computer System Multiplying Current Variable Injection Rate with a Constant to Set New Variable Injection Rate at Source Node
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Application:
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Programmably Sliceable Switch-Fabric Unit and Methods of Use
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Variably Delayable Transmission of Packets Between Independently Clocked Source, Intermediate, and Destination Circuits While Maintaining Orderly and Timely Processing in One or Both of the Intermediate and Destination Circuits
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Application:
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Method and Structure for Allocating Sites in an Expanded Scb Array
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Parallel Scsi Host Adapter and Method for Fast Capture of Shadow State Data
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Overmold Cable Terminator
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Method and Apparatus for Raid Load Balancing
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Asynchronous Fault-Tolerant Enclosure Services Interface
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Application:
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Programmable Logic Datapath That May Be Used in a Field Programmable Device
Raid 1 Write Mirroring Method for Host Adapters
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Raid 1 Read Mirroring Method for Host Adapters
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Extended Frequency Range Voltage-Controlled Oscillator
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Equalization for Crosspoint Switches
Hardware Circuit and Method for Automatically Configuring on-the-Fly a Sub-Unit in a Scsi Message
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10/068,650 →
Structure and Method for Message Snooping in Scsi Bus Expanders
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Application:
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Variable Read/Write Margin High-Performance Soft-Error Tolerant Sram Bit Cell
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Method for Providing a Configuration Extensible Markup Language (Xml) Page to a User for Configuring an Xml Based Storage Handling Contoller
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On-Chip Inter-Subsystem Communication Including Concurrent Data Traffic Routing
Apparatus and Method for Metering and Marking Data in a Communication System
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Apparatus and Method for High Speed Sampling or Testing of Data Signals Using Automated Testing Equipment
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Method and Apparatus for Combination Host Bus Adapter
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Generic Packet Parser
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Method and Apparatus for Minimizing Option Rom Bios Code
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Application:
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Method and Apparatus to Detect a Timeout Condition for a Data Item Within a Process
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Methods for Configuring Separate Accessibility of Each Channel of a Dual Channel Scsi Chip
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Data Stream Permutation Applicable to Large Dimensions
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Method and Apparatus for Dual Porting a Single Port Serial Ata Disk Drive
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Method for Managing Memory Space During System Initialization
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Software Based System and Method for I/O Chip Hiding of Processor Based Controllers from Operating System
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Systems and Methods for Monitoring and Displaying I/O Data for Plurality of I/O Devices
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Apparatus and Methods for Increasing Bandwidth in an Infiniband Switch
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Apparatus and Methods for Combinational Error Detection in an Infiniband Switch
Efficient Variably-Channelized Sonet Multiplexer and Payload Mapper
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10/176,230 →
Method and Apparatus for Raid on Memory
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Application:
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Structure for Handling Packetized Scsi Protocol Data Overruns in a Multi-Data Channel Host Adapter
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Method and Structure for Handling Packetized Scsi Protocol Data Overruns in a Multi-Data Channel Host Adapter
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Apparatus and Method for Efficient Data Transport Using Transparent Framing Procedure
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High Speed I-O Loopback Testing with Low Speed Dc Test Capability
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Infiniband Layer 4 Router and Methods for Implementing Same in an Infiniband Based External Storage Device
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High-Efficiency Mixed Voltage/Current Mode Output Driver
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Method for Snooping Raid 1 Write Transactions by a Storage Device
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10/210,250 →
Method for Snooping Raid 1 Read Transactions by a Storage Device
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Method and Apparatus for the Synchronous Control of a Serial Interface
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System and Method for Frequency and Phase Modulating Data on a Scsi Bus or a Serial Scsi Link
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Efficient Virtual Concatenation Datapath for Sonet/Sdh
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Differential Delay Compensation
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Data Format Conversion for Virtual Concatenation Processing
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Buffer Management Architecture and Method for an Infiniband Subnetwork
Disk Array Fault Tolerant Method and System Using Two-Demensional Parity
Host Adapter Integrated Data Fifo and Data Cache and Method for Improved Host Adapter Sourcing Latency
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Application:
10/280,955 →
Two-Dimensional Execution Queue for Host Adapters
Patent:
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Application:
10/295,618 →
Method and System for Three Disk Fault Tolerance in a Disk Array
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10/295,726 →
Method and System for a Disk Fault Tolerance in a Disk Array Using Rotating Parity
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10/300,981 →
Flexible Data Transfer to and from External Device of System-On-Chip
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
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10/302,782 →
Method and System for Four Disk Fault Tolerance in a Disk Array
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Application:
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Method and Apparatus for Relocating Raid Meta Data
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Application:
10/318,587 →
Switch-Management Agent Trap Scheme in an Infiniband-Architecture Switch
Fifo Buffer Depth Estimation for Asynchronous Gapped Payloads
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Multicast Connection Scheduling in Time:Space:Time Switching Fabrics
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10/323,939 →
Fast, Deterministic Exact Match Look-Ups in Large Tables
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7,043,494 →
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10/353,723 →
Method and/or Apparatus Distributing Variable-Sized Data Units to Variable Destinations
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Load Balancing Multicast Connection Scheduling in 3-Stage Tdm Fabrics
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Method and System for Five-Disk Fault Tolerance in a Disk Array
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Application:
10/365,382 →
Joint Equalization and Timing Acquisition for Rz Signals
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Application:
10/384,585 →
Cascaded Jitter Frequency Shifting Delta-Sigma Modulated Signal Synchronization Mapper
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Application:
10/424,718 →
High Speed I/O Pad and Pad/Cell Interconnection for Flip Chips
Method for Aborting Data Transfer Commands
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Application:
10/429,005 →
Dequeuing from a Host Adapter Two-Dimensional Queue
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Application:
10/443,241 →
Raid 6 Disk Array with Prime Number Minus One Disks
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Application:
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Method for Boot Recovery
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Equalizer and Equalization Method for Return-to-Zero Signals
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10/618,017 →
I20 Command and Status Batching
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No Single Point of Failure Raid Box Using Sata Drives
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10/665,846 →
Programmable Logic Device Partitioning Method for Application Specific Integrated Circuit Prototyping
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10/693,285 →
Methods for Expansive Netboot
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Application:
10/712,710 →
Simulation of Complex System Architecture
Flexible Adaptation Engine for Adaptive Transversal Filters
Networked Processor for a Pipeline Architecture
Cache Memory Architecture and Associated Microprocessor Design
Method and Apparatus for Vendor-Specific Device Communication
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7,210,090 →
Application:
10/733,152 →
System and Method for Authentication of Embedded Raid on a Motherboard
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Application:
10/740,971 →
System and Method for Authentication of Embedded Raid on a Motherboard Having Input/Output Processor
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Application:
10/741,234 →
Method and Architecture for the Extraction and/or Insertion of Sonet or Sdh Path Overhead Data Streams
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10/753,446 →
Overlapping Jumping Window for Sonet/Sdh Bit Error Rate Monitoring
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Application:
10/755,403 →
Boundary Scan Cell and Methods for Integrating and Operating the Same
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7,305,603 →
Application:
10/762,799 →
Egress Selection Switch Architecture with Power Management
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Application:
10/765,945 →
Method and Apparatus for Packet Grooming and Aggregation
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Hardware I/O Control Block Array for Mirrored Data Transfers
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Application:
10/779,351 →
Method for Configuring a Single Hardware I/O Control Block Architecture for Use with Both Mirrored and Non-Mirrored Data Transfers
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6,871,238 →
Application:
10/779,416 →
Hardware I/O Control Block Structure for Mirrored and Non-Mirrored Data Transfers
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10/779,417 →
Apparatus for Performing Device Communication and Method for Operating the Same
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Method and Apparatus for Handling Sas/Sata Communication Deadlock
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Application:
10/795,183 →
Alignment Signal Control Apparatus and Method for Operating the Same
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7,373,541 →
Application:
10/800,048 →
Multi-Function Bypass Port and Port Bypass Circuit
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7,474,612 →
Application:
10/805,441 →
Memory Egress Self Selection Architecture
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7,492,760 →
Application:
10/812,958 →
Wired Endian Method and Apparatus for Performing the Same
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Application:
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In-Phase and Quadrature Decision Feedback Equalizer
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7,339,989 →
Application:
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Systems and Methods for Actively-Peaked Current-Mode Logic
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Application:
10/820,381 →
Methods of and Apparatus for Efficient Buffer Cache Utilization
Method and Apparatus for Reducing Current Demand Variations in Large Fan-Out Trees
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10/830,031 →
Method and System for Error Correction Over Serial Link
Method for Dedicated Netboot
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Single Driver for Multifunctional Scsi Chips
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10/850,203 →
Serial Data Validity Monitor
Method and apparatus for interconnection offlow-controlled communication
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10/871,334 →
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Auto-Configuration of Raid Systems
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10/889,006 →
Dequeuing from a Host Adapter Two-Dimensional Queue
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Systems and Methods for Jitter Analysis of Digital Signals
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Method and System for Asynchronously Transferring Data
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System and Method for Opportunistic Request-Grant Switching
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Application:
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Efficient Strictly Non-Blocking Multicast Switch Architecture for Time Division Multiplexed Traffic
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Methods and Apparatus for a Segregated Interface for Parameter Configuration in a Multi-Path Failover System
Built in Self Test (Bist) for High-Speed Serial Transceivers
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10/998,090 →
Systems and Methods for a Built in Test Circuit for Asynchronous Testing of High-Speed Transceivers
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Method and Apparatus for Balanced Disk Access Load Distribution
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Method and Apparatus for Accessing a Striped Configuration of Disks
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System and Method for Authentication of Embedded Raid on a Host Raid Card
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Raid 6 Disk Array Architectures
Decision Feedback Equalizer (Dfe) for Jitter Reduction
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11/074,966 →
Cache Synchronization in a Raid Subsystem Using Serial Attached Scsi and/or Serial Ata
Systems and Methods for Signature Circuits
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Quadrature Modulation Compensation
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Active Biasing in Metal Oxide Semiconductor (Mos) Differential Pairs
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Expansion of Cross-Domain Addressing for Pci-Express Packets Passing Through Non-Transparent Bridge
Pre-Cursor Inter-Symbol Interference Cancellation
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Apparatus for Real-Time Arbitration Between Masters and Requestors and Method for Operating the Same
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7,975,086 →
Application:
11/152,965 →
Apparatus for Masked Arbitration Between Masters and Requestors and Method for Operating the Same
Patent:
7,979,615 →
Application:
11/152,993 →
Cyclic Redundancy Check Circuit for Use with Self-Synchronous Scramblers
Cyclic Redundancy Check Circuit for Use with Self-Synchronous Scramblers
Dequeuing from a Host Adapter Two-Dimensional Queue
Patent:
7,484,017 →
Application:
11/170,293 →
Method and System for Configuring an Interconnect Device
Systems and Methods for Translation of Signal Levels Across Voltage Domains
Patent:
7,205,820 →
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11/177,853 →
Systems and Methods for a Self-Organizing Analog-to-Digital Converter
Patent:
7,161,523 →
Application:
11/219,417 →
Advanced Adaptive Pre-Distortion in a Radio Frequency Transmitter
Patent:
7,471,739 →
Application:
11/231,165 →
Automatic Generators for Verilog Programming
Patent:
7,770,147 →
Application:
11/234,623 →
Clock and Data Recovery Locking Technique for Large Frequency Offsets
Patent:
7,738,617 →
Application:
11/237,622 →
Asic Functional Specification Parser
Patent:
7,765,502 →
Application:
11/241,661 →
Systems and Methods for Reducing Frequency-Offset Induced Jitter
Patent:
7,558,357 →
Application:
11/257,711 →
Automated Device Testing Using Intertwined Stimulus-Generation and Response Validation Specifications for Managing Dut's That Generate Out-of-Order Responses
Serial Tunneling Protocol (Stp) Flow Control in Sas Expanders Without Sata Link State Machine
Patent:
7,496,700 →
Application:
11/326,505 →
Serial Attached Scsi Broadcast Primitive Processor Filtering for Loop Architectures
Patent:
8,089,902 →
Application:
11/326,508 →
Data Subset Selection Algorithm for Reducing Data-Pattern Autocorrelations
Patent:
7,876,866 →
Application:
11/339,554 →
Method and Apparatus for Routing in Sas Using Logical Zones
Patent:
7,668,925 →
Application:
11/341,573 →
Method and Apparatus for Broadcast Primitive Filtering in Sas
Patent:
8,116,226 →
Application:
11/341,574 →
Virtual Concatenation of Pdh Signals
DMA engine for protocol processing
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Publication:
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Feedback Priority Modulation Rate Controller
Device and Method for Address Matching with Post Matching Limit Check and Nullification
Patent:
7,779,197 →
Application:
11/382,475 →
Binary Base Address Sorting Method and Device with Shift Vector
Patent:
7,647,438 →
Application:
11/382,480 →
Method and Apparatus for Finding Subset Maxima and Minima in Sas Expanders and Related Devices
Patent:
7,958,295 →
Application:
11/389,025 →
Connection Management in Serial Attached Scsi (Sas) Expanders
Patent:
7,584,319 →
Application:
11/390,182 →
Hierarchical Device Spin-Up Control for Serial Attached Devices
Patent:
7,474,926 →
Application:
11/390,264 →
Packets Transfer Device Having Data Absorbing Buffers with Elastic Buffer Capacities
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
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7,260,365 →
Application:
11/392,180 →
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
Patent:
7,200,367 →
Application:
11/392,286 →
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
Patent:
7,177,603 →
Application:
11/392,439 →
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
Patent:
7,340,223 →
Application:
11/392,453 →
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
Patent:
7,295,815 →
Application:
11/392,460 →
Binary Base Address Search Device and Method
Patent:
7,454,554 →
Application:
11/395,715 →
Method and Device for Base Address Sorting and Entry into Base Address Registers
Patent:
7,694,025 →
Application:
11/395,918 →
Systems and Methods for the Dynamic Range Compression of Multi-Bearer Single-Carrier and Multi-Carrier Waveforms
Systems and Methods for the Reduction of Peak to Average Signal Levels of Multi-Bearer Single-Carrier and Multi-Carrier Waveforms
Method and apparatus for SAS open address frame processing in SAS expanders
Application:
11/412,944 →
Method and Apparatus for Detection of High-Speed Electrical Signals
Device for Concurrent Limit Validity Check
Patent:
7,634,586 →
Application:
11/422,190 →
On-Chip Inter-Subsystem Communication Including Concurrent Data Traffic Routing
Cache Memory Architecture with System Controller Device That Compares Cache Tags to Memory Addresses Received from Microprocessor
Packets Transfer Device That Intelligently Accounts for Variable Egress Channel Widths When Scheduling Use of Dispatch Bus by Egressing Packet Streams
Efficient Strip-Down and Re-Alignment of Ingressing Physical Layer/Data Layer Packets in an Aggregated Pci-Express Port Having Eight Lanes
Compact Cmos Esd Layout Techniques with Either Fully Segmented Salicide Ballasting (Fssb) in the Source and/or Drain Regions
Patent:
7,646,063 →
Application:
11/451,610 →
Method of Rate Snooping in a Sas/Sata Environment
Patent:
7,774,424 →
Application:
11/470,042 →
Command Switching for Multiple Initiator Access to a Sata Drive
Patent:
7,739,432 →
Application:
11/470,078 →
Apparatus for Interconnecting Hosts with Storage Devices
Patent:
8,127,059 →
Application:
11/470,112 →
Systems and Methods for Speed Binning of Integrated Circuts
Patent:
7,539,893 →
Application:
11/513,624 →
Bus Interface for Transfer of Multiple Sonet/Sdh Rates Over a Serial Backplane
Method and Apparatus for Distributed Topology Function in Serial Attached Small Computer System Interface (Sas)
Patent:
8,797,918 →
Application:
11/536,250 →
Stabilized Digital Timing Recovery Using Low-Complexity Equalizer
Patent:
7,656,945 →
Application:
11/538,346 →
Sequencer Cache and Method for Operating the Same
Method of Improving Over Protocol-Required Scheduling Tables While Maintaining Same
Apparatus and Method for Detecting Extended Error Bursts
Patent:
7,802,167 →
Application:
11/669,479 →
Systems and Methods for Esd Protection
Patent:
7,719,806 →
Application:
11/672,304 →
Method for Boot Recovery
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7,480,819 →
Application:
11/677,491 →
Device and Method for Handling Catastrophic Routing
Patent:
7,756,014 →
Application:
11/677,697 →
Constant Gain Digital Predistortion Controller for Linearization of Non-Linear Amplifiers
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7,904,033 →
Application:
11/678,863 →
Systems and Methods of Reducing Power Consumption of Digital Integrated Circuits
Patent:
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Post-Distortion Filter for Reducing Sensitivity to Receiver Nonlinearities
Patent:
7,912,151 →
Application:
11/688,685 →
Systems and Methods for Actively-Peaked Current-Mode Logic
Patent:
7,288,971 →
Application:
11/691,859 →
Method and Apparatus for Extended Addressing in a Fiber Channel Arbitrated Loop
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7,860,103 →
Application:
11/693,939 →
Variably Delayable Transmission of Packets Between Independently Clocked Source, Intermediate, and Destination Circuits While Maintaining Orderly and Timely Processing in One or Both of the Intermediate and Destination Circuits
Configurable Voltage Mode Transmitted Architecture with Common-Mode Adjustment and Novel Pre-Emphasis
Forward Error Correction with Self-Synchronous Scramblers
Patent:
7,913,151 →
Application:
11/753,409 →
Pulse Output Direct Digital Synthesis Circuit
Integrated Memory for Storing Egressing Packet Data, Replay Data and to-Be Egressed Data
Adaptive Signal Decompression
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7,936,835 →
Application:
11/777,819 →
Systems and Methods for Hitless Equipment Protection
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7,656,791 →
Application:
11/780,361 →
Method for Managing Memory Space During System Initialization
Delay Measurements and Calibration Methods and Apparatus for Distributed Wireless Systems
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7,940,667 →
Application:
11/829,403 →
Programmably Sliceable Switch-Fabric Unit and Methods of Use
Background Calibration Technique for Pipelined a/D Converters Using Simplified Histogram-Based Testing
Patent:
7,460,045 →
Application:
11/839,097 →
Method for Enhancing Linearity of a Transistor Amplifier Using Switched Capacitive Loads
Patent:
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Application:
11/846,959 →
Continuous Wave Based Bias Method and Apparatus for Minimizing Mos Transistor Distortion
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7,679,448 →
Application:
11/847,535 →
Integrated Memory for Storing Egressing Packet Data, Replay Data and to-Be Egressed Data
Method and Apparatus for Conversion of an Arbitration Table into Count Values to Control the Distribution of Resources
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Application:
11/854,495 →
Method of Skipping Nullified Packets During Mass Replay from Replay Buffer
Method and Apparatus for Raid on Memory
Out-Of-Channel Received Signal Strength Indication (Rssi) for Rf Front End
Patent:
7,979,041 →
Application:
11/952,463 →
On-Chip Shared Memory Based Device Architecture
Patent:
7,743,191 →
Application:
11/961,402 →
Galois Field Multiplier System and Method
Patent:
8,099,655 →
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Method and System for Analyzing Signal Waveforms
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8,024,142 →
Application:
11/961,543 →
Pattern-Based Dc Offset Correction
Patent:
7,622,987 →
Application:
12/019,535 →
Techniques to Control Amplifier Gain Over Process, Voltage, and/or Temperature (Pvt) Variations
Patent:
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Application:
12/037,340 →
Loaded Parallel Stub Common Mode Filter for Differential Lines Carrying High Rate Digital Signals
Patent:
7,956,704 →
Application:
12/038,433 →
Lowpass-Bandstop Common Mode Filter for Differential Lines Carrying High Rate Digital Signals
Patent:
7,812,693 →
Application:
12/038,503 →
Clock and Data Recovery Sampler Calibration
Patent:
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Application:
12/040,585 →
Tuning of Analog Filters
Patent:
7,714,643 →
Application:
12/044,636 →
Controlled Discovery of San-Attached Scsi Devices and Access Control via Login Authentication
Run-Length Based Spectral Analysis
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8,019,028 →
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12/055,948 →
Interference Erasure Using Soft Decision Weighting of the Viterbi Decoder Input in Ofdm Systems
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8,019,029 →
Application:
12/062,392 →
Adaptive Predistortion of Non-Linear Amplifiers with Burst Data
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Application:
12/099,369 →
Phase pre-emphasis for a serial data transmitter
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8,315,303 →
Application:
12/110,210 →
Power Optimized Adc for Wireless Transceivers
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Application:
12/114,322 →
Apparatus and Method to Adjust Power and Performance of Integrated Circuits
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12/129,408 →
Cache Synchronization in a Raid Subsystem Using Serial Attached Scsi and/or Serial Ata
Variable-Length Digitally-Controlled Delay Chain with Interpolation-Based Tuning
Systems and Methods for Automatic Provisioning of Storage and Operating System Installation from Pre-Existing Iscsi Target
Wideband Mixer
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8,396,441 →
Application:
12/170,176 →
Egress Selection Switch Architecture with Power Management
Patent:
8,085,764 →
Application:
12/175,243 →
System and Method for Deskewing Data Transmitted Through Data Lanes
Patent:
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Application:
12/188,195 →
Method of Tracking Arrival Order of Packets into Plural Queues
Dma Address Translation Scheme and Cache with Modified Scatter Gather Element Including Sg List and Descriptor Tables
Patent:
8,176,252 →
Application:
12/203,455 →
Semiconductor Device for Electrostatic Discharge Protection
Patent:
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Application:
12/242,225 →
Semiconductor Device for Latch-Up Prevention
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7,777,248 →
Application:
12/242,413 →
Multi-Queue System and Method for Deskewing Symbols in Data Streams
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8,161,210 →
Application:
12/264,158 →
Data Aggregation System and Method for Deskewing Data at Selectable Data Rates
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Application:
12/264,184 →
Active Biasing in Metal Oxide Semiconductor (Mos) Differential Pairs
Patent:
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Application:
12/265,609 →
Logical Address Direct Memory Access with Multiple Concurrent Physical Ports and Internal Switching
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Application:
12/277,194 →
Method and Apparatus for Archiving Data During Unexpected Power Loss
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Application:
12/326,845 →
Integrated Tunable Rf Notch Filter
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8,428,203 →
Application:
12/349,328 →
Serial Tunneling Protocol (Stp) Flow Control in Sas Expanders Without Sata Link State Machine
Patent:
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Application:
12/355,362 →
Equalizer for Heavily Clipped or Compressed Communications Signals
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Application:
12/359,046 →
Method and Apparatus for Serdes Jitter Tolerance Improvement
Patent:
8,116,409 →
Application:
12/361,436 →
Hard Disk Drive with Attached Solid State Drive Cache
Hot-Pluggable Differential Signaling Driver
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7,898,295 →
Application:
12/407,269 →
High Speed Phase Frequency Detector
Patent:
7,940,088 →
Application:
12/415,426 →
Transceiver Gain Calibration
Patent:
8,134,410 →
Application:
12/488,919 →
Echo Cancellation for Duplex Radios
Patent:
7,916,671 →
Application:
12/504,295 →
Connection Management in Serial Attached Scsi (Sas) Expanders
Patent:
8,095,722 →
Application:
12/507,859 →
Standby Disk Spin Up Control in Disk Array System Using Expander Device
Patent:
8,296,513 →
Application:
12/545,114 →
Adaptively Intelligent Storage Controller and Associated Methods
Patent:
9,256,542 →
Application:
12/558,925 →
Multi-Client Content Addressable Memory Access Control Method
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8,533,389 →
Application:
12/559,951 →
Methods for Forming Fully Segmented Salicide Ballasting (Fssb) in the Source and/or Drain Region
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Application:
12/606,691 →
Jitter Attenuation with a Fractional-N Clock Synthesizer
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7,986,190 →
Application:
12/610,074 →
Method and System for Controlling Count Information in Generic Mapping Procedure
Patent:
8,340,134 →
Application:
12/612,397 →
Congestion Management for a Packet Switch
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8,174,969 →
Application:
12/625,491 →
Reduction of Electromagnetic Interference for Differential Signals
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8,004,330 →
Application:
12/627,345 →
Dsp-Based Diagnostics for Monitoring a Serdes Link
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8,467,436 →
Application:
12/627,667 →
Equalizer Adaptation for Heavily Compressed or Clipped Communications Signals
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8,644,369 →
Application:
12/628,894 →
High-Performance Ingress Buffer for a Packet Switch
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8,391,302 →
Application:
12/630,811 →
Predictive Flow Control for a Packet Switch
Patent:
8,295,293 →
Application:
12/639,938 →
Packet Switch with Enqueue Structure for Ordering Packets
Patent:
8,284,790 →
Application:
12/701,472 →
Error Detection and Correction in Data and Control Words
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8,413,006 →
Application:
12/705,304 →
Pipeline Scheduler for a Packet Switch
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Application:
12/710,592 →
Predistortion with Integral Crest-Factor Reduction and Reduced Observation Bandwidth
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8,446,979 →
Application:
12/715,745 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
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8,261,167 →
Application:
12/720,487 →
Power Optimized Adc for Wireless Transceivers
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Application:
12/748,754 →
Auto-Configuration of Raid Systems
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8,090,981 →
Application:
12/758,659 →
Variable-Length Digitally-Controlled Delay Chain with Interpolation-Based Tuning
Method and Apparatus for Improving the Signal Integrity of High-Speed Serial Data Receivers Using Coupled Inductors
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8,947,840 →
Application:
12/781,335 →
Input/Output Interfacing with Low Power
Patent:
8,018,251 →
Application:
12/791,547 →
Clock and Data Recovery Locking Technique for Large Frequency Offsets
Patent:
8,139,702 →
Application:
12/815,045 →
Pci Express Switch and Method for Multi-Port Non-Transparent Switching
Patent:
8,429,325 →
Application:
12/852,399 →
System and Method for Generating Locator Polynomials
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8,327,243 →
Application:
12/857,391 →
Bch Data Correction System and Method
Patent:
8,397,144 →
Application:
12/913,716 →
System and Method for Scatter Gather Cache Processing
Patent:
8,495,301 →
Application:
12/939,128 →
Reduction of Correlated Channel Impairments
Patent:
8,611,473 →
Application:
12/969,402 →
Method and Apparatus for Extended Addressing in a Fiber Channel Arbitrated Loop
Patent:
8,483,226 →
Application:
12/973,275 →
Post-Distortion Filter for Reducing Sensitivity to Receiver Nonlinearities
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8,300,733 →
Application:
12/985,206 →
Logical Address Direct Memory Access with Multiple Concurrent Physical Ports and Internal Switching
Patent:
8,271,700 →
Application:
13/012,296 →
Forward Error Correction with Self-Synchronous Scramblers
Patent:
8,020,077 →
Application:
13/019,734 →
Nonvolatile Memory Controller with Two-Stage Error Correction Technique for Enhanced Reliability
Patent:
8,707,122 →
Application:
13/023,336 →
Management of Linked Lists Within a Dynamic Queue System
Patent:
9,262,554 →
Application:
13/027,777 →
Nonvolatile Memory Controller with Host Controller Interface for Retrieving and Dispatching Nonvolatile Memory Commands in a Distributed Manner
Patent:
8,588,228 →
Application:
13/052,008 →
Interrupt Technique for a Nonvolatile Memory Controller
Patent:
8,554,968 →
Application:
13/052,388 →
System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique
Patent:
8,601,346 →
Application:
13/052,835 →
Adaptive Signal Decompression
Patent:
8,396,149 →
Application:
13/079,310 →
Mirrored Cache Protection
System and Method for Routing a Data Message Through a Message Network
Patent:
8,656,071 →
Application:
13/107,265 →
Multi-Mode Driver with Multiple Transmitter Types and Method Therefor
Data Regeneration Apparatus and Method for Pci Express
Patent:
8,599,913 →
Application:
13/195,685 →
Error Correction Code Technique for Improving Read Stress Endurance
Patent:
8,694,855 →
Application:
13/287,443 →
Method and Apparatus for Queue Ordering in a Multi-Engine Processing System
Patent:
8,559,439 →
Application:
13/288,437 →
System and Method for Multiengine Operation with Super Descriptor in Sas/Sata Controller Wherein Portion of Super-Descriptor Is Executed Without Intervention of Initiator
Patent:
8,762,609 →
Application:
13/288,599 →
Method and Apparatus for a Multi-Engine Descriptor Controller for Distributing Data Processing Tasks Across the Engines
Patent:
8,601,169 →
Application:
13/288,619 →
Methods and Apparatus for Sas Controllers with Link List Based Target Queues
Patent:
9,256,521 →
Application:
13/288,637 →
Apparatus and Method for Driving a Transistor
Patent:
8,624,641 →
Application:
13/288,866 →
Scalable High-Swing Transmitter with Rise and/or Fall Time Mismatch Compensation
Patent:
8,446,173 →
Application:
13/288,875 →
Apparatus and Method for Generating a Bias Voltage
Patent:
8,547,140 →
Application:
13/288,881 →
Reconfigurable Scan Chain Connectivity to Enable Flexible Device I/O Utilization
Patent:
8,533,546 →
Application:
13/309,208 →
Shuffler Error Correction Code System and Method
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8,694,849 →
Application:
13/330,573 →
Methods and Apparatus to Extract Data Encoded in Media Content
System and Method for Algorithmic Tcam Packet Classification
Patent:
8,856,203 →
Application:
13/369,202 →
Decoupling and Pipelining of Multiplexer Loop in Parallel Processing Decision-Feedback Circuits
Patent:
8,699,558 →
Application:
13/404,754 →
Dynamic Resource Allocation for Serial Attached Scsi Devices
Patent:
8,843,671 →
Application:
13/406,390 →
Search Table for Data Networking Matching
Patent:
9,020,953 →
Application:
13/414,383 →
Nonvolatile Memory Controller with Concatenated Error Correction Codes
Patent:
8,656,257 →
Application:
13/434,770 →
Nonvolatile Memory Controller with Error Detection for Concatenated Error Correction Codes
Patent:
8,621,318 →
Application:
13/435,572 →
Hard Disk Drive with Attached Solid State Drive Cache
Operation Methods in an Ethernet Passive Optical Network That Includes a Network Unit with Multiple Entities
Forward Error Correction with Extended Effective Block Size
Control and Coordination of Oduflex Bandwidth Resizing Operation
Patent:
8,854,963 →
Application:
13/466,679 →
Systems and Methods for Storing Data in Page Stripes of a Flash Drive
Patent:
9,176,812 →
Application:
13/477,568 →
Systems and Methods for Low Latency, High Reliability Error Correction in a Flash Drive
Patent:
8,788,910 →
Application:
13/477,595 →
Systems and Methods for Redundantly Storing Error Correction Codes in a Flash Drive with Secondary Parity Information Spread Out Across Each Page of a Group of Pages
Patent:
9,021,336 →
Application:
13/477,598 →
Systems and Methods for Transparently Varying Error Correction Code Strength in a Flash Drive
Patent:
8,972,824 →
Application:
13/477,599 →
Systems and Methods for Adaptively Selecting from Among a Plurality of Error Correction Coding Schemes in a Flash Drive for Robustness and Low Latency
Patent:
9,183,085 →
Application:
13/477,600 →
Systems and Methods for Recovering Data from Failed Portions of a Flash Drive
Patent:
9,021,333 →
Application:
13/477,601 →
Systems and Methods for Adaptively Selecting Among Different Error Correction Coding Schemes in a Flash Drive
Patent:
9,021,337 →
Application:
13/477,629 →
Systems and Methods for Initializing Regions of a Flash Drive Having Diverse Error Correction Coding (Ecc) Schemes
Patent:
8,996,957 →
Application:
13/477,633 →
System and Method for Tolerating a Failed Page in a Flash Device
Patent:
9,047,214 →
Application:
13/477,635 →
Systems and Methods for Reclaiming Flash Blocks of a Flash Drive
Patent:
8,793,556 →
Application:
13/477,845 →
Measuring Impairments of Digitized Signals in Data and Timing Recovery Circuits
Patent:
8,855,179 →
Application:
13/479,733 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
Patent:
8,386,897 →
Application:
13/483,640 →
Method of Reducing Current Leakage in a Device and a Device Thereby Formed
Acceleration of Phase and Frequency Tracking for Low-Latency Timing Recovery
Patent:
8,670,512 →
Application:
13/540,962 →
Gain Calibration for a Mueller-Muller type Timing Error Detector
Patent:
8,693,596 →
Application:
13/549,030 →
Parallel Replica Cdr to Correct Offset and Gain in a Baud Rate Sampling Phase Detector
Patent:
8,942,334 →
Application:
13/549,134 →
Timing and Data Recovery in Feed-Forward Equalization
Patent:
8,867,598 →
Application:
13/585,409 →
Interleaved Digital to Analog Conversion
Patent:
8,773,296 →
Application:
13/624,719 →
Post-Distortion Filter for Reducing Sensitivity to Receiver Nonlinearities
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8,582,701 →
Application:
13/662,282 →
Method and Apparatus for an Aggregated Non-Transparent Requester Id Translation for a Pcie Switch
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8,917,734 →
Application:
13/681,257 →
Method and System for Controlling Count Information in Generic Mapping Procedure
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8,848,743 →
Application:
13/689,532 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
Distributed Electrostatic Discharge Protection Circuit
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9,019,669 →
Application:
13/720,048 →
Adaptive Signal Decompression
Patent:
8,687,723 →
Application:
13/740,113 →
Flexible Routing Engine for a Pci Express Switch and Method of Use
Patent:
9,025,495 →
Application:
13/743,225 →
Method and Apparatus for Translated Routing in an Interconnect Switch
Patent:
8,995,302 →
Application:
13/743,281 →
Method for Estimating and Correcting a Carrier Frequency Offset Over Dispersive but Spectrally Flat Channels
Patent:
8,989,316 →
Application:
13/746,219 →
Method and Apparatus for Mapped I/O Routing in an Interconnect Switch
Patent:
9,146,890 →
Application:
13/750,991 →
Apparatus and Method for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System Using Strong Log-Likelihood (Llr) Values
Patent:
9,128,858 →
Application:
13/752,757 →
Apparatus and Method Based on Ldpc Codes for Adjusting a Correctable Raw Bit Error Rate Limit in a Memory System
Patent:
9,092,353 →
Application:
13/752,885 →
Sas/Sata Store-and-Forward Buffering for Serial-Attached-Scsi (Sas) Storage Network
Patent:
8,924,610 →
Application:
13/753,255 →
Background Calibration of Threshold Errors in Analog to Digital Converters
Patent:
8,779,952 →
Application:
13/766,855 →
Background Calibration of Aperture Center Errors in Analog to Digital Converters
Patent:
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13/766,948 →
Methods and Apparatus for Signal Equalization in Dual Polarization Multiplexed Optical Communication Systems
Patent:
8,923,460 →
Application:
13/767,092 →
Link Selection in a Bonding Protocol
Patent:
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13/780,733 →
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8,866,519 →
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Layer Specific Attenuation Factor Ldpc Decoder
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Method and Apparatus for Driving a Laser Diode
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System and Method for Lifetime Specific Ldpc Decoding
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Method and Apparatus for Changing the Gain of a Radio Frequency Signal
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Power Saving for Fifo Buffer Without Performance Degradation
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13/796,431 →
System and Method for Adaptive Check Node Approximation in Ldpc Decoding
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13/797,444 →
High Speed Gain and Phase Recovery in Presence of Phase Noise
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8,938,037 →
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13/798,970 →
Phase-Locked Loop Based Clock Generator and Method for Operating Same
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Method and Apparatus for Sampling Point Optimization
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Reed-Solomon Decoder
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Programmable Passive Peaking Equalizer
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Multi-Rate Control Loop for a Digital Phase Locked Loop
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Link Negotiation Method for Enabling Communication Between Serial Attached Small Computer Interface (Sas) Storage Devices
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System and Method for Network Switching
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Equalization Adaptation Using Timing Detector
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Method and Apparatus to Control the Effective Gain of a Statistically Calibrated Analog to Digital Converter
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Method and Apparatus for Digital Post-Distortion Compensation of Signal Non-Linearities
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Multiplexing Low-Order to High-Order Odu Signals in an Optical Transport Network
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Justification Insertion and Removal in Generic Mapping Procedure in an Optical Transport Network
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Frame Delineation Method for a Generic Framing Procedure
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Demultiplexing High-Order to Low-Order Odu Signals in an Optical Transport Network
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Gfp Frame Filter
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High Bandwidth Gfp Demapper
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Method and Apparatus for Equalizing Distortion in a Digital Pre-Distortion Observation Path
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Systems and Methods for Mapping for Solid-State Memory
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Systems and Methods for Storing Data for Solid-State Memory
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Systems and Methods for Decoding Data for Solid-State Memory
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Systems and Methods for Reclaiming Memory for Solid-State Memory
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Equalizer for Heavily Clipped or Compressed Communications Signals
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Transmitter Output Impedance Calibration for Output Rise and Fall Time Equalization and Edge Rate Control
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Transmitter Data Path Single-Ended Duty Cycle Correction for Emi Reduction
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System and Method for Avoiding Error Mechanisms in Layered Iterative Decoding
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System and Method for Ldpc Decoding Having Reduced Memory Storage Requirements
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Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 29, 2013
From: ADAPTEC, INC.
To: PMC-SIERRA, INC.
Reel/Frame 030899/0567 →
Security Interest in Patents
Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
Change of Name
Nov 1, 2013
From: SIERRA SEMICONDUCTOR CORPORATION
To: PMC-SIERRA, INC.
Reel/Frame 031544/0250 →
Change of Name
Nov 1, 2013
From: PMC-SIERRA, INC.
To: DELAWARE PMC-SIERRA, INC.
Reel/Frame 031544/0254 →
Change of Name
Nov 1, 2013
From: DELAWARE PMC-SIERRA, INC.
To: PMC-SIERRA, INC.
Reel/Frame 031544/0306 →