Hot-pluggable differential signaling driver
View Patent ↗Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The absence of an explicit near-end driver termination improves efficiency, while replica biasing controls output voltage swing levels. Hot-pluggable compatibility is achieved by a reduction in power-off leakage current and short circuit current protection.
1. An apparatus for differential signaling, the apparatus comprising:
a replica bias circuit comprising a replica NMOS transistor and a replica PMOS transistor;
an explicit resistor having a resistance of about N times a characteristic impedance intended to be driven by a main driver circuit, wherein the explicit resistor is operatively coupled in a current path between sources of the replica NMOS transistor and the replica PMOS transistor, wherein N is greater than 1;
the main driver circuit comprising a driver NMOS transistor and a driver PMOS transistor and steering switches;
wherein the driver NMOS transistor is N times larger than the replica NMOS transistor, wherein a source of the driver NMOS transistor is configured to source current to a load via the steering switches;
wherein the driver PMOS transistor is N times larger than the replica PMOS transistor, and is configured to sink current from the load via the steering switches;
wherein outputs of the steering switches comprises a differential output of the main driver circuit, and wherein control of the steering switches controls the differential output data;
a biasing circuit configured to bias the replica NMOS transistor such that the source of the replica NMOS transistor is biased relative to a first reference level V HIGH and configured to bias the replica PMOS transistor such that the source of the replica PMOS transistor is biased relative to second reference level V LOW different from the first reference level, wherein gate and drain voltages of the replica NMOS transistor and the driver NMOS transistor are coupled for replica biasing, and wherein gate and drain voltages of the replica PMOS transistor and the driver PMOS transistor are coupled for replica biasing; and
a protection control circuit and protection switches, wherein the protection control circuit is configured to control the protection switches, wherein in a normal operating mode, the protection switches permit the biasing circuit to bias the driver NMOS transistor and the driver PMOS transistor, and wherein in a protected mode of operation, the protection switches cut off the driver NMOS transistor and the driver PMOS transistor.
2. An apparatus for differential signaling, the apparatus comprising:
a replica bias circuit comprising a replica NMOS transistor and a replica PMOS transistor;
an explicit resistor having a resistance of about N times a characteristic impedance intended to be driven b a main driver circuit wherein the ex a licit resistor is operatively coupled in a current path between sources of the replica NMOS transistor and the replica PMOS transistor, wherein N is greater than 1;
the main driver circuit comprising a driver NMOS transistor and a driver PMOS transistor and steering switches;
wherein the driver NMOS transistor is N times larger than the replica NMOS transistor, wherein a source of the driver NMOS transistor is configured to source current to a load via the steering switches;
wherein the driver PMOS transistor is N times larger than the replica PMOS transistor, and is configured to sink current from the load via the steering switches;
wherein outputs of the steering switches comprises a differential output of the main driver circuit, and wherein control of the steering switches controls the differential output data; and
a biasing circuit configured to bias the replica NMOS transistor such that the source of the replica NMOS transistor is biased relative to a first reference level V HIGH and configure to bias the replica PMOS transistor such that the source of the replica PMOS transistor is biased relative to second reference level V LOW different from the first reference level, wherein gate and drain voltages of the replica NMOS transistor and the driver NMOS transistor are coupled for replica biasing, and wherein gate and drain voltages of the replica PMOS transistor and the driver PMOS transistor are coupled for replica biasing, wherein the biasing circuit comprises a first biasing circuit and a second biasing circuit:
wherein the first biasing circuit comprises a first differential circuit having a positive input, a negative input, and an output, wherein the positive input is referenced to the first reference level, wherein the output is operatively coupled to a gate of the replica NMOS transistor, and wherein the source of the replica NMOS transistor is operatively coupled to the negative input, wherein the first biasing circuit further comprises a first level shift circuit disposed in the signal path between the output of the first differential circuit and the gate of the replica NMOS transistor and a first steering replica switch disposed in the signal path between the source of the replica NMOS transistor and the negative input, wherein the first steering replica switch is configured to replica a first portion of the voltage drop of the steering switch; and
wherein the second biasing circuit comprises a second differential circuit having a positive input, a negative input, and an output, wherein the positive input is referenced to the second reference level, wherein the output is operatively coupled to a gate of the replica PMOS transistor, and wherein the source of the replica PMOS transistor is operatively coupled to the negative input, wherein the second biasing circuit further comprises a second level shift circuit disposed in the signal path between the output of the second differential circuit and the gate of the replica PMOS transistor and a second steering replica switch disposed in the signal path between the source of the replica PMOS transistor and the negative input, wherein the second steering replica switch is configured to replica a second portion of the voltage drop of the steering switch.
3. A method of differential signaling, the method comprising:
biasing a replica NMOS transistor and a replica PMOS transistor such that the source of the replica NMOS transistor is biased relative to a first reference level V HIGH and such that the source of the replica PMOS transistor is biased relative to second reference level V LOW different from the first reference level;
operatively coupling an explicit resistor in a current path between sources of the replica NMOS transistor and the replica PMOS transistor, wherein the explicit resistor has a resistance of about N times a characteristic impedance intended to be driven by a main driver circuit, wherein N is greater than 1;
biasing a gate and drain of a driver NMOS transistor with a gate voltage and a drain voltage of the replica NMOS transistor, wherein the driver NMOS transistor is N times larger than the replica NMOS transistor, wherein a source of the driver NMOS transistor is configured to source current to a load via the steering switches;
biasing a gate and drain of a driver PMOS transistor with a gate voltage and drain voltage of the replica PMOS transistor, wherein the driver PMOS transistor is N times larger than the replica PMOS transistor, and is configured to sink current from the load via the steering switches;
generating a differential output of the main driver circuit at outputs of steering switches, wherein control of the steering switches controls the differential output data, wherein the steering switches, the driver NMOS transistor, and the driver PMOS transistor are part of the main driver circuit; and
detecting a short condition, and cutting off the driver NMOS transistor and the driver PMOS transistor at least during the short condition.
4. An apparatus for differential signaling, the apparatus comprising:
means for biasing a replica NMOS transistor and a replica PMOS transistor such that the source of the replica NMOS transistor is biased relative to a first reference level V HIGH and such that the source of the replica PMOS transistor is biased relative to second reference level V LOW different from the first reference level;
an explicit resistor in a current path between sources of the replica NMOS transistor and the replica PMOS transistor, wherein the explicit resistor has a resistance of about N times a characteristic impedance intended to be driven by a main driver circuit, wherein N is greater than 1;
means for biasing a gate and drain of a driver NMOS transistor with a gate voltage and a drain voltage of the replica NMOS transistor, wherein the driver NMOS transistor is N times larger than the replica NMOS transistor, wherein a source of the driver NMOS transistor is configured to source current to a load via the steering switches;
means for biasing a gate and drain of a driver PMOS transistor with a gate voltage and drain voltage of the replica PMOS transistor, wherein the driver PMOS transistor is N times larger than the replica PMOS transistor, and is configured to sink current from the load via the steering switches;
means for generating a differential output of the main driver circuit at outputs of steering switches, wherein control of the steering switches controls the differential output data, wherein the steering switches, the driver NMOS transistor, and the driver PMOS transistor are part of the main driver circuit; and
means for detecting a short condition, and means for cutting off the driver NMOS transistor and the driver PMOS transistor at least during the short condition.
5. The apparatus of claim 1 , wherein N is in a range from 5 to 20.
6. The apparatus of claim 1 , wherein the explicit resistor is integrated into an integrated circuit.
7. The apparatus of claim 1 , wherein the circuit is configured to carry digital data.
8. The apparatus of claim 1 , wherein each of the steering switches is an NMOS transistor.
9. The apparatus of claim 1 , wherein the protection control circuit further comprises a comparator circuit configured to compare each line of the differential output of the main driver circuit to a voltage reference to determine whether or not a fault exists, the protection control circuit further comprising pullup resistors coupled to each line of the differential output, wherein the pullup resistors are active at least when a fault has been detected, wherein the pullup resistors permit reset of the protection control circuit.
10. The apparatus of claim 9 , wherein the pullup resistors are active at least when a fault corresponding to a short to ground is detected, wherein the protection control circuit further comprises pulldown resistors coupled to each line of the differential output, wherein the pulldown resistors are active at least when a short to V DD has been detected, wherein the pulldown resistors permit reset of the protection control circuit.
11. The apparatus of claim 1 , wherein the biasing circuit comprises a first biasing circuit and a second biasing circuit:
wherein the first biasing circuit comprises a first differential circuit having a positive input, a negative input, and an output, wherein the positive input is referenced to the first reference level, wherein the output is operatively coupled to a gate of the replica NMOS transistor, and wherein the source of the replica NMOS transistor is operatively coupled to the negative input; and
wherein the second biasing circuit comprises a second differential circuit having a positive input, a negative input, and an output, wherein the positive input is referenced to the second reference level, wherein the output is operatively coupled to a gate of the replica PMOS transistor, and wherein the source of the replica PMOS transistor is operatively coupled to the negative input.
12. The apparatus of claim 1 , further comprising a feedback circuit configured to control an output impedance of at least the driver NMOS transistor and the driver PMOS transistor.
13. The method of claim 3 , wherein N is in a range from 5 to 20.
14. The method of claim 3 , wherein each of the steering switches is an NMOS transistor.
15. The apparatus of claim 4 , wherein N is in a range from 5 to 20.
16. The apparatus of claim 4 , wherein each of the steering switches is an NMOS transistor.
17. The apparatus of claim 2 , wherein N is in a range from 5 to 20.
18. The apparatus of claim 2 , wherein the explicit resistor is integrated into an integrated circuit.
19. The apparatus of claim 2 , wherein the circuit is configured to carry digital data.
20. The apparatus of claim 2 , wherein each of the steering switches is an NMOS transistor.
21. The apparatus of claim 2 , further comprising a feedback circuit configured to control an output impedance of at least the driver NMOS transistor and the driver PMOS transistor.