Semiconductor device for latch-up prevention
View Patent ↗A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.
1. A semiconductor latch up prevention device comprising:
a substrate;
first and second wells formed in the substrate;
an injector region formed in the first well, the injector region including at least one injector;
a Silicon Controlled Rectifier (SCR) formed in the second well, the SCR including at least first and second parasitic bipolar transistors dominantly of opposite connectivity types;
a natively doped region provided between the SCR and the injector region, the natively doped region having a resistance at least about 10 times higher than a resistance of the first and second wells; and
a guard ring formed in the first well between the injector region and the natively doped region;
the substrate, the first and second wells, and the natively doped region being of the same connectivity type, and the substrate and the natively doped region having substantially the same doping.
2. The device of claim 1 , wherein the natively doped region is an epitaxial layer.
3. The device of claim 1 , wherein the natively doped region is provided in the form of one or more strips, and wherein the first well and the second well are electrically connected to each other and form one well.
4. The device of claim 1 , wherein the resistance of the natively doped region is in the range of about 10 to about 100 times higher than the resistance of the first well.
5. The device of claim 1 , wherein the resistance of the natively doped region is more than 100 times higher than the resistance of the first well.
6. The device of claim 1 , wherein the natively doped region surrounds the injector region, the first well, and the guard ring.
7. The device of claim 1 , wherein the natively doped region surrounds the second well and the SCR.
8. The device of claim 1 , wherein the connectivity type of the substrate, the wells and the natively doped region is P-type.
9. The device of claim 1 , wherein the connectivity type of the substrate, the wells and the natively doped region is N-type.
10. The device of claim 6 , further comprising a third well of the same connectivity type, the third well being electrically connected to the first well, and being provided between the guard ring and the natively doped region.
11. A semiconductor latch up prevention device comprising:
a substrate;
first and second wells formed in the substrate;
an injector region formed in the first well, the injector region including at least one injector;
a first guard ring provided in the first well adjacent the injector region;
a first parasitic bipolar transistor formed in the second well, the first parasitic bipolar transistor being dominantly of the first connectivity type;
a second guard ring formed in the second well adjacent the first parasitic bipolar transistor;
a natively doped region provided between the second guard rind and the first well, the natively doped region having a resistance at least about 10 times higher than a resistance of the first and second wells;
a second parasitic bipolar transistor formed in the first well, the second parasitic bipolar transistor being dominantly of a second connectivity type so as to form a Silicon Controlled Rectifier (SCR) with the first parasitic bipolar transistor;
a third guard ring formed in the first well between the natively doped region and the second parasitic bipolar transistor;
the substrate, the first and second wells, and the natively doped region being of the same connectivity type, and the substrate and the natively doped region having substantially the same doping;
wherein the first parasitic bipolar transistor is provided in between the second parasitic bipolar transistor and the injector region, and wherein the natively doped region surrounds the first parasitic bipolar transistor, the second well and the second guard ring so as to concurrently isolate the first parasitic bipolar transistor, the second well and the second guard ring from the second parasitic bipolar transistor and from the injector region.
12. The device of claim 11 , further comprising a third well of the same connectivity type as the second well, that is electrically connected to the second well, and is provided between the second guard ring and the natively doped region.
13. The device of claim 11 , wherein the first parasitic bipolar transistor is dominantly P-type and the second parasitic bipolar transistor is dominantly N-type.
14. The device of claim 11 , wherein the first parasitic bipolar transistor is dominantly N-type and the second parasitic bipolar transistor is dominantly P-type.
15. The device of claim 11 , wherein the natively doped region is an epitaxial layer.
16. The device of claim 11 , wherein the natively doped region is provided in the form of one or more strips and wherein the first well and the second well are electrically connected to each other and form one well.
17. The device of claim 11 , wherein the resistance of the natively doped region is in the range of about 10 to about 100 times higher than the resistance of the first well.
18. The device of claim 11 , wherein the resistance of the natively doped region is more than 100 times higher than the resistance of the first well.
19. The device of claim 11 , wherein the connectivity type of the substrate, the wells and the natively doped region is P-type.
20. The device of claim 11 , wherein the connectivity type of the substrate, the wells and the natively doped region is N-type.
21. A semiconductor latch up prevention device comprising:
a substrate of a first connectivity type;
a first well of a second connectivity type formed in the substrate, the first well including at least a first implanted region of the first connectivity type and a second implanted region of the second connectivity type, the implanted regions of the first well being arranged for connection to first polarity rail;
a second well of the first connectivity type formed in the substrate including a third implanted region of the first connectivity type;
a third well of the first connectivity type formed in the substrate, the third well including at least a fourth implanted region of the first connectivity type and a fifth implanted region of the second connectivity type, the second and third wells being electrically connected to the substrate and forming one terminal therewith; and
a natively doped region provided between the second and third wells, the natively doped region having a resistance at least about 10 times higher than the second and third wells, the implanted regions of the second and third wells being arranged for connection to a second polarity rail;
the first implanted region forming a first parasitic bipolar transistor dominantly of the first connectivity type with the first well and the second well, and the fifth implanted region forming a second parasitic bipolar transistor dominantly of the second connectivity type with the first well and the third well, wherein the natively doped region creates a separation resistance that helps the current received upon activation of the first parasitic bipolar transistor to flow through the third implanted region of the second well away from the second parasitic bipolar transistor in order to avoid latch up.
22. The device of claim 21 , wherein the first well comprises a sixth implanted region of the first connectivity type for connection to a circuit pad.
23. The device of claim 21 , wherein the third well comprises a seventh implanted region of the second connectivity type for connection to a circuit pad.
24. The device of claim 21 , wherein the first and fifth implanted regions are diffusions.
25. The device of claim 21 , wherein the third and the fourth implanted regions are guard rings.
26. The device of claim 21 , wherein the natively doped region is an epitaxial layer.
27. The device of claim 21 , wherein the natively doped region is provided in the form of one or more strips and wherein the second well and the third well are electrically connected to each other and form one well.
28. The device of claim 21 , wherein the natively doped region is provided in the form of a ring that surrounds the first and the second wells.
29. The device of claim 21 , wherein the natively doped region is provided in the form of a ring that surrounds the third well.
30. The device of claim 21 , wherein the natively doped region is provided in the form of two rings, one ring that surrounds the first and second wells, and one ring that surrounds the third well.
31. The device of claim 21 , wherein the resistance of the natively doped region is in the range of about 10 to about 100 times higher than the resistance of the second and third wells.
32. The device of claim 21 , wherein the resistance of the natively doped region is more than 100 times higher than the resistance of the second and third wells.
33. The device of claim 21 , wherein the first connectivity type is P-type and the second connectivity type is N-type.
34. The device of claim 21 , wherein the first connectivity type is N-type and the second connectivity type is P-type.
35. The device of claim 33 , wherein the first polarity rail is a positive power rail, and the second polarity rail is a negative power rail.
36. The device of claim 34 , wherein the first polarity rail is a negative power rail, and the second polarity rail is a positive power rail.