Patent Assignment
Reel/Frame 030899/0567
Assignment of Assignor's Interest
Recorded: 2013-07-29
Pages: 21
Assignor
ADAPTEC, INC.
Executed: 2010-06-08
Assignee
PMC-SIERRA, INC.
1380 BORDEAUX DRIVE, SUNNYVALE, CALIFORNIA, 94089
Covered Properties
(219)
Prefetch/Prestore Mechanism for Peripheral Controllers with Shared Internal Bus
Patent:
5,557,750 →
Application:
07/963,583 →
Scsi Host Adapter with Shared Command and Data Buffer
Patent:
5,732,223 →
Application:
07/963,584 →
A Progammably Configurable Host Adapter Integrated Circuit Including a Risc Processor
Patent:
5,659,690 →
Application:
07/964,532 →
Interface and Control Circuit for Regulating Data Flow in a Scsi Initiator with Multiple Host Bus Interface Selection
Patent:
5,544,326 →
Application:
08/029,910 →
System for Starting and Completing a Data Transfer for a Subsequently Received Autotransfer Command After Receiving a First Scsi Data Transfer Command That Is Not Autotransfer
Patent:
5,634,081 →
Application:
08/205,002 →
Scsi Command Descriptor Block Parsing State Machine
Patent:
5,504,868 →
Application:
08/205,003 →
Scsi Host Adapter Integrated Circuit Utilizing a Sequencer Circuit to Control at Least One Non-Data Scsi Phase Without Use of Any Processor
Patent:
5,655,147 →
Application:
08/229,864 →
Method for Accessing a Sequencer Control Block by a Host Adapter Integrated Circuit
Patent:
5,564,023 →
Application:
08/269,463 →
Global Parity Symbol for Interleaved Reed-Solomon Coded Data
Patent:
5,642,366 →
Application:
08/270,858 →
Status Indicator for a Host Adapter
Patent:
5,657,455 →
Application:
08/301,458 →
Error Generation Circuit for Testing a Digital Bus
Patent:
5,701,409 →
Application:
08/392,442 →
System for Generating Second Interrupt Signal for Data Transfer Completion for a First Scsi Data Transfer Command That Is Not Autotransfer
Patent:
5,640,593 →
Application:
08/462,719 →
System for Supplying Initiator Identification Information to Scsi Bus in a Reselection Phase of an Initiator Before Completion of an Autotransfer Command
Patent:
5,845,154 →
Application:
08/463,333 →
Method for Receiving a First Scsi Command, Subsequent Receiving Second Scsi Command and Starting Data Transfer, Reconnecting and Performing Data Transfer for First Scsi Command
Patent:
5,752,083 →
Application:
08/463,617 →
Method of Flagging the Completion of a Second Command Before the Completion of a First Command from the Same Initiator in a Scsi Controller
Patent:
5,603,066 →
Application:
08/463,649 →
System for Storing Initiator, Queue Tag and Logical Block Information, Disconnecting from Target If Command Is Not Auto Transfer, Reconnecting and Performing Data Transfer
Patent:
5,781,803 →
Application:
08/465,075 →
Integrated Circuit with a Serial Port Having Only One Pin
Patent:
5,826,068 →
Application:
08/482,529 →
A Deskew Circuit in a Host Interface Circuit
Patent:
5,748,806 →
Application:
08/486,084 →
A Method of Operation of a Host Adapter Integrated Circuit
Patent:
5,838,950 →
Application:
08/486,096 →
Method and Apparatus for Implementing an Application Programming Interface for a Communications Bus
Patent:
5,815,678 →
Application:
08/503,078 →
Preserving Configuration Information in a Scam Based Scsi System
Patent:
5,692,134 →
Application:
08/532,919 →
A Serial Port Having Only a Single Terminal for Information Transfer to and from an Integrated Circuit
Patent:
5,920,708 →
Application:
08/592,800 →
Method for Specifying Concurrent Execution of a String of I/O Command Blocks in a Chain Structure
Patent:
5,850,567 →
Application:
08/615,476 →
Host Adapter System Including an Integrated Pci Buffer Controller and Xor Function Circuit
Patent:
5,881,250 →
Application:
08/615,477 →
Hardware Method for Verifying That an Area of Memory Has Only Zero Values
Patent:
5,867,732 →
Application:
08/615,478 →
Method for Concurrently Executing a Configured String of Concurrent I/O Command Blocks Within a Chain Concurrently to Perform a Raid 5 I/O Operation
Patent:
5,892,969 →
Application:
08/615,479 →
Chain Manager for Use in Executing a Chain of I/O Command Blocks
Patent:
5,768,621 →
Application:
08/616,817 →
Method for Specifying Execution of Only One of a Pair of I/O Command Blocks in a Chain Structure
Patent:
5,797,034 →
Application:
08/616,836 →
Method for Enhancing Performance of a Raid 1 Read Operation Using a Pair of I/O Command Blocks in a Chain Structure
Patent:
5,758,187 →
Application:
08/616,838 →
I/O Command Block Chain Structure in a Memory
Patent:
5,812,877 →
Application:
08/616,846 →
Method for Sequencing Execution of I/O Command Blocks in a Chain Structure by Setting Hold-Off Flags and Configuring a Counter in Each I/O Command Block
Patent:
5,923,896 →
Application:
08/617,990 →
A Method of Enabling and Disabling a Data Function in an Integrated Circuit
Patent:
5,991,861 →
Application:
08/617,991 →
Global Parity Symbol for Interleaved Reed-Solomon Coded Data
Patent:
5,872,799 →
Application:
08/687,009 →
Error Generation Circuit for Testing a Digital Bus
Patent:
5,978,934 →
Application:
08/797,802 →
Interleaved Burst Xor Using a Single Memory Pointer
Patent:
5,946,707 →
Application:
08/808,526 →
Shift Register-Based Xor Accumulator Engine for Generating Parity in a Data Processing System
Patent:
5,896,406 →
Application:
08/829,044 →
Write Synchronization System on a Headerless Format Magnetic Disk Device
Patent:
6,084,739 →
Application:
08/829,432 →
Methods and Apparatuses for Automatic Bank Switching in a Host Adapter Memory
Patent:
6,003,017 →
Application:
08/866,427 →
External I/O Controller System for an Independent Access Parity Disk Array
Patent:
6,012,123 →
Application:
08/872,019 →
Status Indicator for a Host Adapter
Patent:
5,978,863 →
Application:
08/876,539 →
Full Enclosure Chassis System with Tool-Free Access to Hot-Pluggable Circuit Boards Therein
Patent:
6,061,250 →
Application:
08/882,170 →
High-Speed Serial Data Cable with Improved Electromagnetic Performance
Patent:
6,109,971 →
Application:
08/887,349 →
Command Interpreter System in an I/O Controller
Patent:
5,931,920 →
Application:
08/906,369 →
System for Copying Iobs from Fifo into I/O Adapter, Writing Data Completed Iob, and Invalidating Completed Iob in Fifo for Reuse of Fifo
Patent:
5,905,905 →
Application:
08/906,765 →
Method and Apparatus for Determining Sector Addresses from Media Having Data Written in a Headerless Format
Patent:
6,023,387 →
Application:
08/926,303 →
Apparatus and Method for Communication Between Integrated Circuits Connected to Each Other by a Single Line
Patent:
6,393,576 →
Application:
08/938,828 →
Integrated Pci Buffer Controller and Xor Function Circuit
Patent:
5,974,530 →
Application:
08/942,373 →
System and Method for Real-Time Data Backup Using Snapshot Copying with Selective Campaction of Backup Data
Patent:
6,061,770 →
Application:
08/963,754 →
File Array Communications Interface for Communicating Between a Host Computer and an Adapter
Patent:
6,009,478 →
Application:
08/963,902 →
File Array Storage Architecture Having File System Distributed Across a Data Processing Platform
Patent:
6,219,693 →
Application:
08/964,304 →
Command Queuing System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,088,740 →
Application:
08/988,016 →
Decentralized File Mapping in a Striped Network File System in a Distributed Computing Environment
Patent:
6,029,168 →
Application:
09/012,267 →
Method for Selectively Booting from a Desired Peripheral Device
Patent:
6,105,130 →
Application:
09/016,764 →
Method and System for Managing Storage Devices Over a Network
Data Transfer Between Small Computer System Interface Systems
Patent:
6,021,454 →
Application:
09/049,522 →
Serial/Parallel Ghz Transceiver with Pseudo-Random Built in Self Test Pattern Generator
Patent:
6,201,829 →
Application:
09/055,197 →
Fault Tolerant Redundant Bus Bridge Systems and Methods
Patent:
6,202,115 →
Application:
09/062,279 →
Redundant Bus Bridge Systems and Methods Using Selectively Synchronized Clock Singals
Patent:
5,991,844 →
Application:
09/062,282 →
Bus Termination Circuitry and Methods for Implementing the Same
Patent:
6,122,689 →
Application:
09/078,346 →
Scatter Gather Memory System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,105,075 →
Application:
09/083,569 →
Scsi Bus Transceiver and Method for Making the Same
Patent:
6,173,344 →
Application:
09/085,671 →
Source-Destination Re-Timed Cooperative Communication Bus
Patent:
6,157,971 →
Application:
09/088,812 →
Host Adapter Having a Snapshot Mechanism
Patent:
6,298,403 →
Application:
09/089,030 →
System for Data Stream Packer and Unpacker Integrated Circuit Which Align Data Stored in a Two Level Latch
Patent:
6,065,066 →
Application:
09/089,039 →
Multiple Access Memory Architecture
Patent:
6,240,482 →
Application:
09/089,044 →
Decoupled Serial Memory Access with Passkey Protected Memory Areas
Patent:
6,148,384 →
Application:
09/089,057 →
Host Adapter Capable of Simultaneously Transmitting and Receiving Data of Multiple Contexts Between a Computer Bus and Peripheral Bus
Patent:
6,202,105 →
Application:
09/089,274 →
A Host Adapter Having Paged Data Buffers for Continuously Transferring Data Between a System Bus and a Peripheral Bus
Patent:
6,070,200 →
Application:
09/089,311 →
Broadcast Command Packet Protocol for Scsi Interface
Patent:
6,477,165 →
Application:
09/097,899 →
Quick Arbitration and Select (Qas) Protocol in Scsi Interface for Configuring a Current Target Device to Assert a Qas Message Code During a Message-in Phase
Patent:
6,058,436 →
Application:
09/098,214 →
Methods of and Apparatus for Monitoring the Termination Status of a Scsi Bus
Patent:
6,154,067 →
Application:
09/130,196 →
Data Alignment System for a Hardware Accelerated Command Interpreter Engine
Patent:
6,145,017 →
Application:
09/130,322 →
Bbs One Bios Image Multicard Support
Patent:
6,061,745 →
Application:
09/133,736 →
Method and Apparatus of Boot Device Switching by a Floppy Disk
Patent:
6,158,002 →
Application:
09/134,760 →
Intelligent Input/Output Target Device Communication and Exception Handling
Patent:
6,182,182 →
Application:
09/181,712 →
Data Fault Tolerance Software Apparatus and Method
Patent:
6,427,212 →
Application:
09/191,943 →
Method for Specifying Concurrent Execution of a String of I/O Command Blocks in a Chain Structure
Patent:
6,157,964 →
Application:
09/205,142 →
Raid Architecture with Two-Drive Fault Tolerance
Patent:
6,353,895 →
Application:
09/250,657 →
Error Generation Circuit for Testing a Digital Bus
Patent:
6,049,894 →
Application:
09/255,406 →
Computer System Storage
Patent:
6,922,688 →
Application:
09/261,708 →
Automatic Multi-Mode Termination
Patent:
6,378,025 →
Application:
09/273,401 →
Storage Area Network Administration
Patent:
7,107,534 →
Application:
09/275,727 →
Method and Apparatus for Creating Formatted Fat Partitions with a Hard Drive Having a Bios-Less Controller
Patent:
6,192,456 →
Application:
09/281,715 →
Universal Option Rom Bios Including Multiple Option Bios Images for Multichip Support and Boot Sequence for Use Therewith
Patent:
6,425,079 →
Application:
09/282,919 →
Ultra Thin and Flexible Scsi Cable and Method for Making the Same
Patent:
6,124,551 →
Application:
09/299,688 →
Method and System for Automatically Determining Maxiumum Data Throughput Over a Bus
Patent:
6,442,628 →
Application:
09/300,818 →
Fast Stack Save and Restore System and Method
Patent:
6,449,709 →
Application:
09/321,329 →
Method for Flashing a Read Only Memory (Rom) Chip of a Host Adapter with Updated Option Rom Bios Code
Patent:
6,282,647 →
Application:
09/324,347 →
Multiple Chip Single Image Bios
Patent:
6,446,139 →
Application:
09/340,539 →
A Scsi Phase Status Register for Use in Reducing Instructions Executed by an on-Chip Sequencer in Asserting a Scsi Ackowledge Signal and Method
Hardware Attention Management Circuit and Method for Parallel Scsi Host Adapters
Patent:
6,415,347 →
Application:
09/344,291 →
Dual-Drive Fault Tolerant Method and System for Assigning Data Chunks to Column Parity Sets
Patent:
6,453,428 →
Application:
09/354,426 →
Self-Healing Computer System Storage
Patent:
6,449,731 →
Application:
09/375,909 →
Object Oriented Fault Tolerance
Patent:
6,742,137 →
Application:
09/376,773 →
Host-Memory Based Raid System, Device, and Method
Patent:
6,526,477 →
Application:
09/389,954 →
Self-Healing Computer System Storage
Patent:
6,530,036 →
Application:
09/439,440 →
Method of Conserving Memory Resources by Directly Decompressing a Compressed Bios Associated with an Option Rom Bios Chip to an Allocated Conventional Memory of System Memory
Patent:
6,567,911 →
Application:
09/455,301 →
System and Method for Parity Caching Based on Stripe Locking in Raid Data Storage
Patent:
6,542,960 →
Application:
09/464,127 →
System and Method for Data Storage Archive Bit Update After Snapshot Backup
Patent:
6,460,054 →
Application:
09/464,250 →
System and Method for Accomplishing Data Storage Migration Between Raid Levels
Patent:
6,510,491 →
Application:
09/465,057 →
Host adapter having paged payload buffers for simultaneously transferring data between a computer bus and a peripheral bus
Patent:
6,279,051 →
Application:
09/531,869 →
Input/Output Communication Networks and Booting Protocols
Patent:
6,691,160 →
Application:
09/552,289 →
Ultra thin and flexible SCSI cable and method for making same
Patent:
6,271,472 →
Application:
09/557,692 →
Intelligent Expansion Rom Sharing Bus Subsystem
Patent:
6,529,989 →
Application:
09/564,105 →
Serial port for a hose adapter integrated circuit using a single terminal
Patent:
6,381,688 →
Application:
09/579,863 →
Serial Bus for Connecting Two Integrated Circuits with Storage for Input / Output Signals
Patent:
6,516,366 →
Application:
09/580,514 →
Two-Dimensional Execution Queue for Host Adapters
Patent:
6,609,161 →
Application:
09/587,538 →
System and Method for Detecting of Unchanged Parity Data
Patent:
6,513,142 →
Application:
09/604,203 →
System and Method for Zeroing Data Storage Blocks in a Raid Storage Implementation
Patent:
6,425,053 →
Application:
09/604,347 →
System and Method for Detection of Disk Storage Blocks Containing Unique Values
Patent:
6,502,169 →
Application:
09/604,348 →
Methods for Associating End Nodes on a Fabric
Patent:
6,769,021 →
Application:
09/613,174 →
Contention-Based Methods for Generating Reduced Number of Interrupts
Patent:
6,718,413 →
Application:
09/650,774 →
File array storage architecture having file system distributed across a data processing platform
Patent:
6,301,605 →
Application:
09/677,034 →
Dual-Channel Scsi Chips and Methods for Configuring Separate Interoperability of Each Channel of the Scsi Chip
Patent:
6,785,746 →
Application:
09/680,834 →
Method and Apparatus for Establishing a Profile Table for Host Bus Adapters
Patent:
7,103,891 →
Application:
09/687,244 →
Method and Apparatus for a Layer Structure Directory for Common Hardware Interface Modules
Patent:
6,775,832 →
Application:
09/687,623 →
Method and Apparatus for Device Discovery
Patent:
7,103,686 →
Application:
09/687,699 →
Method and Apparatus for Address Mapping
Patent:
6,748,459 →
Application:
09/690,120 →
Controller Fault Recovery System for a Distributed File System
Patent:
6,725,392 →
Application:
09/691,579 →
Method and System for Flow Control During the Data Out Phase of the Packetized Scsi Protocol
Patent:
6,769,037 →
Application:
09/745,034 →
Method and Structure for Supporting Flow Control by a Scsi Initiator During the Data Out Phase of the Packetized Scsi Protocol
Patent:
7,047,327 →
Application:
09/745,035 →
Method and Structure for Supporting Flow Control by a Scsi Target During the Data Out Phase of the Packetized Scsi Protocol
Patent:
6,842,798 →
Application:
09/745,036 →
Method and Structure for Supporting Data Streaming by a Scsi Initiator During the Data in Phase of the Packetized Scsi Protocol
Patent:
6,826,646 →
Application:
09/745,106 →
Methods for Managing Host Adapter Settings
Patent:
7,149,978 →
Application:
09/752,504 →
Method and Apparatus for Intelligent Failover in a Multi-Path System
Patent:
6,769,071 →
Application:
09/768,859 →
Method and Apparatus for a Segregated Interface for Parameter Configuration in a Multi-Path Failover System
Patent:
6,823,477 →
Application:
09/768,860 →
Intelligent Load Balancing for a Multi-Path Storage System
Patent:
6,802,021 →
Application:
09/768,957 →
I/O Subsystem Topology Discovery Method
Patent:
6,816,915 →
Application:
09/798,100 →
Automatic Addressing of Expanders in I/O Subsystem
Patent:
6,754,720 →
Application:
09/798,275 →
Methods for Assigning Addresses to Expanded Devices in I/O Subsystem
Patent:
6,751,693 →
Application:
09/798,278 →
Expander Device for Isolating Bus Segments in I/O Subsystem
Patent:
6,948,024 →
Application:
09/846,975 →
Expander Device and Method for Resetting Bus Segments in I/O Subsystem Segmented with Expanders
Patent:
6,862,642 →
Application:
09/858,321 →
Method and Apparatus for Scalable Error Correction Code Generation Performance
Method and System for Accessing an Expanded Scb Array
Patent:
6,845,439 →
Application:
09/872,830 →
Sparse Byte Enable Indicator for High Speed Memory Access Arbitration Method and Apparatus
Method and Apparatus for Post Boot-Up Domain Validation
Patent:
6,813,648 →
Application:
09/898,214 →
Method and Apparatus for Improved Raid 1 Write Performance in Low Cost Systems
Methods for Optimizing Memory Resources During Initialization Routines of a Computer System
Patent:
6,865,669 →
Application:
09/910,580 →
Structure and Method for Linking Scatter/Gather List Segments for Host Adapters
Patent:
7,062,501 →
Application:
09/925,135 →
Method and Apparatus for a Virtual Memory File System
Patent:
7,017,018 →
Application:
09/957,097 →
Method and Apparatus for Extending Storage Functionality at the Bios Level
Patent:
6,904,497 →
Application:
09/962,980 →
A Congestion Management in a Distributed Computer System Multiplying Current Variable Injection Rate with a Constant to Set New Variable Injection Rate at Source Node
Patent:
7,016,971 →
Application:
09/980,760 →
Method and Structure for Allocating Sites in an Expanded Scb Array
Patent:
6,978,336 →
Application:
10/002,869 →
Parallel Scsi Host Adapter and Method for Fast Capture of Shadow State Data
Patent:
6,801,975 →
Application:
10/002,887 →
Overmold Cable Terminator
Patent:
6,814,588 →
Application:
10/010,512 →
Method and Apparatus for Raid Load Balancing
Patent:
6,886,074 →
Application:
10/010,846 →
Asynchronous Fault-Tolerant Enclosure Services Interface
Patent:
7,206,953 →
Application:
10/022,040 →
Raid 1 Write Mirroring Method for Host Adapters
Patent:
6,701,385 →
Application:
10/051,907 →
Raid 1 Read Mirroring Method for Host Adapters
Patent:
6,728,791 →
Application:
10/051,960 →
Hardware Circuit and Method for Automatically Configuring on-the-Fly a Sub-Unit in a Scsi Message
Patent:
7,016,999 →
Application:
10/068,650 →
Structure and Method for Message Snooping in Scsi Bus Expanders
Patent:
6,804,739 →
Application:
10/068,651 →
Method for Providing a Configuration Extensible Markup Language (Xml) Page to a User for Configuring an Xml Based Storage Handling Contoller
Patent:
7,007,158 →
Application:
10/077,466 →
Method and Apparatus for Combination Host Bus Adapter
Patent:
7,085,877 →
Application:
10/108,063 →
Method and Apparatus for Minimizing Option Rom Bios Code
Patent:
6,971,003 →
Application:
10/115,734 →
Methods for Configuring Separate Accessibility of Each Channel of a Dual Channel Scsi Chip
Patent:
6,880,033 →
Application:
10/125,238 →
Method and Apparatus for Dual Porting a Single Port Serial Ata Disk Drive
Patent:
7,089,345 →
Application:
10/131,387 →
Method for Managing Memory Space During System Initialization
Patent:
7,234,047 →
Application:
10/133,812 →
Software Based System and Method for I/O Chip Hiding of Processor Based Controllers from Operating System
Patent:
6,970,986 →
Application:
10/153,549 →
Systems and Methods for Monitoring and Displaying I/O Data for Plurality of I/O Devices
Patent:
6,832,271 →
Application:
10/155,814 →
Method and Apparatus for Raid on Memory
Patent:
7,293,138 →
Application:
10/185,307 →
Structure for Handling Packetized Scsi Protocol Data Overruns in a Multi-Data Channel Host Adapter
Patent:
7,028,117 →
Application:
10/185,875 →
Method and Structure for Handling Packetized Scsi Protocol Data Overruns in a Multi-Data Channel Host Adapter
Patent:
7,085,864 →
Application:
10/186,102 →
Infiniband Layer 4 Router and Methods for Implementing Same in an Infiniband Based External Storage Device
Patent:
7,860,941 →
Application:
10/198,337 →
Method for Snooping Raid 1 Write Transactions by a Storage Device
Patent:
7,080,198 →
Application:
10/210,250 →
Method for Snooping Raid 1 Read Transactions by a Storage Device
Patent:
6,988,166 →
Application:
10/210,594 →
Method and Apparatus for the Synchronous Control of a Serial Interface
Patent:
6,829,663 →
Application:
10/225,905 →
System and Method for Frequency and Phase Modulating Data on a Scsi Bus or a Serial Scsi Link
Patent:
7,127,002 →
Application:
10/226,587 →
Disk Array Fault Tolerant Method and System Using Two-Demensional Parity
Host Adapter Integrated Data Fifo and Data Cache and Method for Improved Host Adapter Sourcing Latency
Patent:
7,024,523 →
Application:
10/280,955 →
Two-Dimensional Execution Queue for Host Adapters
Patent:
6,742,053 →
Application:
10/295,618 →
Method and System for Three Disk Fault Tolerance in a Disk Array
Patent:
6,792,391 →
Application:
10/295,726 →
Method and System for a Disk Fault Tolerance in a Disk Array Using Rotating Parity
Patent:
7,188,270 →
Application:
10/300,981 →
Method and System for Four Disk Fault Tolerance in a Disk Array
Patent:
7,093,159 →
Application:
10/317,493 →
Method and Apparatus for Relocating Raid Meta Data
Patent:
6,985,996 →
Application:
10/318,587 →
Method and System for Five-Disk Fault Tolerance in a Disk Array
Patent:
7,062,604 →
Application:
10/365,382 →
Method for Aborting Data Transfer Commands
Patent:
6,934,770 →
Application:
10/429,005 →
Dequeuing from a Host Adapter Two-Dimensional Queue
Patent:
6,789,134 →
Application:
10/443,241 →
Raid 6 Disk Array with Prime Number Minus One Disks
Patent:
7,103,716 →
Application:
10/607,381 →
Method for Boot Recovery
Patent:
7,219,257 →
Application:
10/608,312 →
I20 Command and Status Batching
Patent:
7,124,207 →
Application:
10/640,936 →
No Single Point of Failure Raid Box Using Sata Drives
Patent:
7,711,793 →
Application:
10/665,846 →
Programmable Logic Device Partitioning Method for Application Specific Integrated Circuit Prototyping
Patent:
7,086,025 →
Application:
10/693,285 →
Methods for Expansive Netboot
Patent:
7,234,053 →
Application:
10/712,710 →
Simulation of Complex System Architecture
Networked Processor for a Pipeline Architecture
Method and Apparatus for Vendor-Specific Device Communication
Patent:
7,210,090 →
Application:
10/733,152 →
System and Method for Authentication of Embedded Raid on a Motherboard
Patent:
7,600,132 →
Application:
10/740,971 →
System and Method for Authentication of Embedded Raid on a Motherboard Having Input/Output Processor
Patent:
7,502,942 →
Application:
10/741,234 →
Boundary Scan Cell and Methods for Integrating and Operating the Same
Patent:
7,305,603 →
Application:
10/762,799 →
Hardware I/O Control Block Array for Mirrored Data Transfers
Patent:
6,862,631 →
Application:
10/779,351 →
Method for Configuring a Single Hardware I/O Control Block Architecture for Use with Both Mirrored and Non-Mirrored Data Transfers
Patent:
6,871,238 →
Application:
10/779,416 →
Hardware I/O Control Block Structure for Mirrored and Non-Mirrored Data Transfers
Patent:
6,934,771 →
Application:
10/779,417 →
Apparatus for Performing Device Communication and Method for Operating the Same
Patent:
7,376,759 →
Application:
10/782,249 →
Method and Apparatus for Handling Sas/Sata Communication Deadlock
Patent:
7,360,119 →
Application:
10/795,183 →
Alignment Signal Control Apparatus and Method for Operating the Same
Patent:
7,373,541 →
Application:
10/800,048 →
Wired Endian Method and Apparatus for Performing the Same
Patent:
7,181,562 →
Application:
10/816,338 →
Methods of and Apparatus for Efficient Buffer Cache Utilization
Single Driver for Multifunctional Scsi Chips
Patent:
7,249,201 →
Application:
10/850,203 →
Auto-Configuration of Raid Systems
Patent:
7,702,948 →
Application:
10/889,006 →
Dequeuing from a Host Adapter Two-Dimensional Queue
Patent:
6,938,102 →
Application:
10/923,596 →
Method and System for Asynchronously Transferring Data
Patent:
6,996,640 →
Application:
10/935,013 →
Methods and Apparatus for a Segregated Interface for Parameter Configuration in a Multi-Path Failover System
Method and Apparatus for Balanced Disk Access Load Distribution
Patent:
7,330,930 →
Application:
11/053,818 →
Method and Apparatus for Accessing a Striped Configuration of Disks
Patent:
7,406,563 →
Application:
11/054,659 →
System and Method for Authentication of Embedded Raid on a Host Raid Card
Patent:
7,836,219 →
Application:
11/054,785 →
Raid 6 Disk Array Architectures
Cache Synchronization in a Raid Subsystem Using Serial Attached Scsi and/or Serial Ata
Apparatus for Real-Time Arbitration Between Masters and Requestors and Method for Operating the Same
Patent:
7,975,086 →
Application:
11/152,965 →
Apparatus for Masked Arbitration Between Masters and Requestors and Method for Operating the Same
Patent:
7,979,615 →
Application:
11/152,993 →
Dequeuing from a Host Adapter Two-Dimensional Queue
Patent:
7,484,017 →
Application:
11/170,293 →
Automatic Generators for Verilog Programming
Patent:
7,770,147 →
Application:
11/234,623 →
Asic Functional Specification Parser
Patent:
7,765,502 →
Application:
11/241,661 →
Sequencer Cache and Method for Operating the Same
Method for Boot Recovery
Patent:
7,480,819 →
Application:
11/677,491 →
Method for Managing Memory Space During System Initialization
Method and Apparatus for Raid on Memory
Systems and Methods for Automatic Provisioning of Storage and Operating System Installation from Pre-Existing Iscsi Target
Method and Apparatus for Archiving Data During Unexpected Power Loss
Patent:
7,954,006 →
Application:
12/326,845 →
Combined Usb Hub Device and Stand
Patent:
484,136 →
Application:
29/151,059 →
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest in Patents
Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
Release of Security Interest
Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
Patent Security Agreement
Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
Release of Security Interest
May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →