ASIC functional specification parser
View Patent ↗A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
1. A computer implemented method for generating a register interface module, comprising method operations of:
accessing a functional specification stored in memory of a computing system;
identifying successive register descriptions within the functional specification;
extracting register information from each of the successive register descriptions;
verifying a name assigned to each of the successive register descriptions is unique among the register descriptions;
generating a register definition file once each name has been verified as being unique and
writing the register definition file to the memory.
2. The method of claim 1 , wherein the register interface module is generated from the register definition file.
3. The method of claim 1 , wherein the method operation of identifying successive register descriptions within the functional specification includes,
parsing text to identify a start to a register description.
4. The method of claim 1 , wherein the method operation of extracting register information from each of the successive register descriptions includes, parsing text constructs to identify a name of each register.
5. The method of claim 4 , further comprising:
identifying from the text constructs, register information selected from the group consisting of an address/mode, a type, a bit name, and a bit location.
6. The method of claim 5 , wherein duplication of one of the address/mode and the bit name among the register descriptions triggers an error signal.
7. The method of claim 1 further comprising:
issuing an error signal if duplicate names are identified among the register descriptions.
8. A computer storage and readable medium having program instructions for generating a register interface module, comprising method operations of:
executing and providing a functional specification for the program instructions;
program instructions for identifying successive register descriptions within the functional specification;
program instructions for extracting register information from each of the successive register descriptions;
program instructions for verifying a name assigned to each of the successive register descriptions is unique among the register descriptions; and
program instructions for generating a register definition file once each name has been verified as being unique.
9. The computer readable medium of claim 8 , wherein the register interface module is generated from the register definition file.
10. The computer readable medium of claim 8 , wherein the program instructions for identifying successive register descriptions within the functional specification includes,
program instructions for parsing text to identify a start to a register description.
11. The computer readable medium of claim 8 , wherein the program instructions for extracting register information from each of the successive register descriptions includes,
program instructions for parsing text constructs to identify a name of each register.
12. The computer readable medium of claim 11 , further comprising:
program instructions for identifying from the text constructs, register information selected from the group consisting of an address/mode, a type, a bit name, and a bit location.
13. The computer readable medium of claim 8 further comprising:
program instructions for issuing an error signal if duplicate names are identified among the register descriptions.
14. The computer readable medium of claim 12 , wherein duplication of one of the address/mode and the bit name among the register descriptions triggers program instructions for generating an error signal.
15. A computing system configured to generate a register interface module during a design of an integrated circuit, comprising:
a central processing unit (CPU);
a memory in communication with the CPU, the memory containing register interface program instructions configured to be executed by the CPU and a functional specification of the integrated circuit, wherein execution of the program instructions cause the processor to perform a method comprising:
identifying successive register descriptions within the functional specification;
extracting register information from each of the successive register descriptions;
verifying a name assigned to each of the successive register descriptions is unique among the register descriptions; and
generating a register definition file once each name has been verified as being unique.
16. The computing system of claim 15 , wherein the functional specification is stored in a text-based format.
17. The computing system of claim 15 , further comprising:
a bus enabling communication between the memory and the CPU.
18. The computing system of claim 15 , wherein text term “REGISTER:” identifies a beginning of each of the register descriptions.
19. The computing system of claim 15 , wherein extracting register information from each of the successive register descriptions includes, parsing text constructs to identify a name of each register.
20. The computing system of claim 19 , further comprising:
identifying from the text constructs, register information selected from the group consisting of an address/mode, a type, a bit name, and a bit location.