Software based system and method for I/O chip hiding of processor based controllers from operating system
View Patent ↗An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.
1. A system for hiding an input/output device from an operating system, comprising:
an input/output chip (IOC) in communication with a bus;
an input/output processor (IOP) in communication with the bus, the IOP configured to control the IOC;
a system bios that provides a window of time wherein the IOP has exclusive access to the bus, exclusive access is provided by allowing no other system element to win arbitration of access to the bus, wherein the IOP configures an IOC memory map register during the window of time such that the configured IOC memory map register allows communication between the IOP and the IOC, and wherein the IOP configures a hide indicator to indicate the IOC should be hidden and the system bios allows other system elements to win arbitration of access to the bus after the IOC is hidden.
2. A system as recited in claim 1 , wherein the system bios configures the hide indicator before the window of time to indicate the IOC should be hidden.
3. A system as recited in claim 2 , wherein the IOP configures the hide indicator during the window of time to indicate the IOC should be exposed, the hide indicator being configured to expose the IOC prior to configuring the IOC memory.
4. A system as recited in claim 3 , wherein the hide indicator is a hide bit.
5. A system as recited in claim 3 , wherein the hide indicator is an IDSEL pin.
6. A system as recited in claim 3 , wherein a system bios provides the window of time using a master arbiter.
7. A system as recited in claim 1 , wherein the system bios provides a new window of time wherein the IOP has exclusive access to the bus in response to an operating system reassigning the IOC memory map register, and wherein the IOP reconfigures the IOC memory map register during the new window of time such that the reconfigured IOC memory map register allows communication between the IOP and the IOC.
8. A method for hiding an input/output device from an operating system, comprising the operations of:
executing a code segment to provide a window of time wherein a specific input/output processor (IOP) has exclusive access to a bus by allowing no other system element to win arbitration of access to the bus;
configuring an IOC memory map register during the window of time using the IOP, the IOC memory being utilized by an input/output chip (IOC);
configuring a hide indicator by the IOP to indicate the IOC should be hidden;
communicating data between the IOP and the IOC using the IOC memory map register; and
executing the code segment to allow other system elements to win arbitration of access to the bus after the IOC is hidden.
9. A method as recited in claim 8 , further comprising the operation of configuring the hide indicator before the window of time to indicate the IOC should be hidden.
10. A method as recited in claim 9 , further comprising the operation of configuring the hide indicator during the window of time to indicate the IOC should be exposed, wherein the hide indicator is configured to expose the IOC prior to configuring the IOC memory map register.
11. A method as recited in claim 10 , wherein the hide indicator is a hide bit.
12. A method as recited in claim 11 , wherein the hide bit is an IDSEL bit.
13. A method as recited in claim 10 , wherein the code segment is a system bios that provides the window of time using a master arbiter.
14. A method as recited in claim 13 , wherein the master arbiter is a peripheral component interconnect (PCI) master arbiter.
15. A computer program embodied on a computer readable medium for hiding an input/output device from an operating system, comprising:
a code segment that provides a window of time wherein a specific input/output processor (IOP) has exclusive access to a bus by allowing no other system element to win arbitration of access to the bus;
a code segment that configures an IOC memory map register during the window of time, the IOC memory map register being utilized by an input/output chip (IOC); and
a code segment that configures a hide indicator to indicate the IOC should be hidden, wherein data is communicated between the IOP and the IOC using the IOC memory map register; and
a code segment that allows other system elements to win arbitration of access to the bus after the IOC is hidden.
16. A computer program as recited in claim 15 , further comprising a code segment that configures the hide indicator before the window of time to indicate the IOC should be hidden.
17. A computer program as recited in claim 16 , further comprising a code segment that configures the hide indicator during the window of time to indicate the IOC should be exposed, wherein the hide indicator is configured to expose the IOC prior to configuring the IOC memory map register.
18. A computer program as recited in claim 17 , wherein the hide bit is an IDSEL bit.
19. A computer program as recited in claim 17 , wherein the hide indicator is an IDSEL pin.
20. A computer program as recited in claim 10 , wherein a system bios includes the code segment that provides the window of time, and wherein the system bios utilizes a master arbiter to facilitate providing the window of time.