Hardware I/O control block structure for mirrored and non-mirrored data transfers
View Patent ↗A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.
1. A hardware I/O control block structure stored in a memory, said hardware I/O control block structure comprising:
one of a read command for a read transaction and a write command for a write transaction to be executed by a target device;
a sister hardware I/O control block field; and
a target identification field wherein upon said sister hardware I/O control block field containing a valid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a mirrored data transaction using said target device identified using information in said target identification field.
2. The hardware I/O control block structure stored in a memory as in claim 1 wherein said hardware I/O control block structure is one of a plurality of hardware I/O control block structures in said memory.
3. The hardware I/O control block structure stored in a memory as in claim 1 wherein upon said sister hardware I/O control block field containing an invalid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a non-mirrored data transaction.
4. The hardware I/O control block structure stored in a memory as in claim 1 wherein said valid value comprises a valid hardware I/O control block identification number.
5. The hardware I/O control block structure stored in a memory as in claim 3 wherein said invalid value comprises a null identification number.
6. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a read transaction.
7. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a write transaction.
8. A system comprising:
a host adapter;
a plurality of target devices coupled to said host adapter; and
a memory coupled to said host adapter, and said memory having stored therein a hardware I/O control block structure comprising:
one of a read command for a read transaction and a write command for a write transaction to be executed by a target device in said plurality of target devices;
a sister hardware I/O control block field; and
a target identification field wherein upon said sister hardware I/O control block field containing a valid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a mirrored data transaction using said target device, in said plurality of target devices, identified using information in said target identification field.
9. The system of claim 8 wherein said hardware I/O control block structure is one of a plurality of hardware I/O control block structures in said memory.
10. The system of claim 8 wherein upon said sister hardware I/O control block field containing an invalid value when said hardware I/O control block structure is a new hardware I/O control block structure, said hardware I/O control block structure is for a non-mirrored data transaction.
11. The system as in claim 8 wherein said valid value comprises a valid hardware I/O control block identification number.
12. The system as in claim 10 wherein said invalid value comprises a null identification number.
13. The system as in claim 8 wherein said mirrored data transaction comprises a read transaction.
14. The system as in claim 8 wherein said mirrored data transaction comprises a write transaction.