IP Library Granted Patent US 7,836,219
Granted Patent B1
US 7,836,219 · App. 11/054,785 · Granted Nov 16, 2010

System and method for authentication of embedded RAID on a host RAID card

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Quick Facts
Patent No.
US 7,836,219
App. No.
11/054,785
Granted
Nov 16, 2010
Kind
B1
Abstract

An invention is provided for authenticating software associated with an embedded device on a motherboard. An embodiment includes executing an option ROM BIOS for the embedded device. If a bit pattern read from a first memory located on the host card does not match a predetermined bit pattern, the option ROM BIOS is terminated. In another embodiment, a first memory address is provided to the address lines of a memory device located on the host card and a first set of data is output from the memory device, followed by a second memory address to output a second set of data. The second memory address is equal to the first memory address plus the maximum addressable size of the memory device. The first set of data is compared to the second data, and the option ROM BIOS is terminated if the first and second sets of data do not match.

Claims (20)

1. A method for authenticating software associated with an embedded device on a host card, comprising the operations of: storing an option ROM BIOS in flash memory on the host card; separately storing during manufacturing of the host card, a predetermined bit pattern in a first memory located on the host card; executing during system startup, the option ROM BIOS for the embedded device; reading, by the option ROM BIOS, a second bit pattern from the first memory; comparing the second bit pattern to the predetermined bit pattern; writing a signature to a second memory located on the host card when the second bit pattern matches the predetermined bit pattern, wherein the option ROM BIOS is terminated if the host card includes the predetermined bit pattern stored in the first memory that does not match the second bit pattern; and continuing post process startup operations even when the option ROM BIOS is terminated.

2. A method as recited in claim 1 , wherein the first memory is a one time programmable (OTP) area of the flash memory on the host card.

3. A method as recited in claim 1 , wherein the first memory is a programmable logic device (PLD).

4. A method for authenticating software associated with an embedded device on a host card, comprising the operations of, executing during system startup, an option ROM BIOS for the embedded device; reading, by the option ROM BIOS, a first bit pattern from a first memory; comparing the first bit pattern to a predetermined bit pattern; writing a signature to a second memory located on the host card when the first bit pattern matches the predetermined bit pattern, wherein the option ROM BIOS is terminated if the host card includes the predetermined bit pattern stored in the first memory that does not match the first bit pattern, wherein the signature is a pre-selected bit pattern for use in authenticating the host card; and continuing post process startup operations even when the option ROM BIOS is terminated.

5. A method as recited in claim 1 , further comprising the operation of checking a device driver for the embedded device every time the device driver is started, wherein if the signature is not present in the second memory the device driver will be terminated, else the device driver continues,

whereby allowing an update of the device driver without restarting the system.

6. A method as recited in claim 5 , wherein the second memory is an electronically erasable programmable read only memory (EEPROM).

7. A system for authenticating software associated with an embedded device on a host card, comprising: a flash memory device storing an option ROM BIOS for the embedded device; a first memory device being programmed during manufacturing of the host card with a predetermined bit pattern; and an electronically erasable programmable read only memory (EEPROM), wherein the option ROM BIOS reads during startup of the option ROM BIOS a second bit pattern from the first memory device and compares the second bit pattern to the predetermined bit pattern, wherein the option ROM BIOS writes a signature to the EEPROM when the second bit pattern matches the predetermined bit pattern, wherein the option ROM BIOS is terminated if the host card includes the predetermined bit pattern stored in the first memory device that does not match the second bit pattern, wherein the system continues post process startup operations even if the option ROM BIOS is terminated.

8. A system as recited in claim 7 , wherein the first memory device is a one time programmable (OTP) area of the flash memory device.

9. A system as recited in claim 7 , wherein the first memory device is a programmable logic device (PLD).

10. A system as recited in claim 7 , wherein the signature is a pre-selected bit pattern for use in authenticating the host card.

11. A system as recited in claim 7 , wherein a device driver for the embedded device is checked every time the device driver is started and the device driver is terminated when the signature is not present in the EEPROM, else the device driver continues.

12. A method for authenticating software associated with an embedded device on a host card, comprising the operations of: executing during system startup, an option ROM BIOS for the embedded device; providing a first memory address to address lines of a memory device located on the host card, wherein a first set of data is output from the memory device; providing a second memory address to address lines of the memory device located on the host card, the second memory address being equal to the first memory address plus the maximum addressable size of the memory device, wherein a second set of data is output from the memory device; comparing the first set of data to the second set of data; writing a signature to a second memory located on the host card when the first set of data matches the second set of data, wherein the option ROM BIOS is terminated if the host card includes the first set of data stored in the memory device that does not match the second set of data stored in the memory device; and continuing post process startup operations even when the option ROM BIOS is terminated.

13. A method as recited in claim 12 , wherein the memory device is a wrap around flash memory device, wherein the first memory address and the second memory address access a same physical memory location.

14. A method as recited in claim 12 , further comprising the operation of checking a device driver for the embedded device every time the device driver is started, wherein if the signature is not present in the second memory the device driver will be terminated, else the device driver continues,

whereby allowing the update of the device driver without restarting the system.

15. A method as recited in claim 14 , wherein the second memory is an electronically erasable programmable read only memory (EEPROM).

16. A method as recited in claim 1 , wherein the host card includes a RAID controller coupled to the flash memory.

17. A method as recited in claim 16 , wherein the RAID controller is coupled to the second memory on the host card.

18. A method as recited in claim 1 , wherein the signature comprises a plurality of bit signatures written to a plurality of addresses in the second memory.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2013
From: ADAPTEC, INC.
To: PMC-SIERRA, INC.
Reel/Frame 030899/0567 →