Methods for configuring separate accessibility of each channel of a dual channel SCSI chip

1. A method for configuring channels of a dual channel SCSI chip, comprising:

setting at least one bit in a first configuration space within a first channel control in the dual channel SCSI chip, the first configuration space being configured to return a device identification information when accessed by an operating system; and

setting at least one bit in a second configuration space within a second channel control in the dual channel SCSI chip, the second configuration space being configured to return data indicating that the second configuration space does not contain any device identification information when accessed by the operating system;

wherein the first channel control is detected and managed by the operating system, and the second channel control is not detected by the operating system and is managed by a device processor.

2. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , wherein the at least one bit in the first configuration space includes a first control bit and the at least one bit in the second configuration space includes a second control bit, the first control bit and the second control bit being capable of determining which of the first channel control and the second channel control are hidden from the operating system.

3. A method for configuring channels of a dual channel SCSI chip as recited in claim 2 , wherein the first control bit is located in register address FFh of the first configuration space and the second control bit is located in register address FFh of the second configuration space.

4. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , wherein the first channel control is a SCSI channel control and the second channel control is a RAID channel control.

5. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , wherein the device identification information includes at least one of a device ID, a vendor ID, a sub device ID, and a sub vendor ID.

6. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , wherein the device processor is a RAID IOP.

7. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , further comprising:

setting a first management bit for the first configuration space from a non-volatile memory.

8. A method for configuring channels of a dual channel SCSI chip as recited in claim 7 , further comprising:

setting a second management bit for the second configuration space from the non-volatile memory.

9. A method for configuring channels of a dual channel SCSI chip as recited in claim 1 , wherein the second configuration space is configured to return a read abort when the operating system requests access to the device identification information.

10. A method for configuring channels of a dual channel SCSI chip, comprising:

setting at least one bit in a first configuration space within a first channel control in the dual channel SCSI chip, the first configuration space being set to return a first device identification information when accessed by an operating system;

setting at least one bit in a second configuration space within a second channel control in the dual channel SCSI chip, the second configuration space set to return a null data indicating that the second configuration space does not contain any device identification information when accessed by the operating system;

returning the first device identification information from the first channel control when the operating system accesses the first configuration space; and

returning a null data from a second channel control when the operating system requests access to the second configuration space;

wherein the first channel control is detected and managed by the operating system, and the second channel control is not detected by the operating system and is managed by a device processor.

11. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , wherein the at least one bit in the first configuration space includes a first control bit and the at least one bit in the second configuration space includes a second control bit, the first control bit and the second control bit being capable of determining which of the first channel control and the second channel control are hidden from the operating system.

12. A method for configuring channels of a dual channel SCSI chip as recited in claim 11 , wherein the first control bit is located in register address FFh of the first configuration space and the second control bit is located in register address FFh of the second configuration space.

13. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , wherein the first channel control is a SCSI channel control and the second channel control is a RAID channel control.

14. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , wherein the device identification information includes at least one of a device ID, a vendor ID, a sub device ID, and a sub vendor ID.

15. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , wherein the device processor is a RAID IOP.

16. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , further comprising:

setting a first management bit for the first configuration space from a non-volatile memory.

17. A method for configuring channels of a dual channel SCSI chip as recited in claim 16 , further comprising:

setting a second management bit for the second configuration space from a non-volatile memory.

18. A method for configuring channels of a dual channel SCSI chip as recited in claim 10 , wherein the second configuration space is configured to return a read abort when the operating system requests access to the device identification information.

19. A method for configuring channels of a dual channel SCSI chip, comprising:

providing a first control bit in a first PCI configuration space of a first channel control and a second control bit in a second PCI configuration space of a second channel control;

determining whether the first control bit is asserted and whether the second control bit is asserted;

when at least one of the first control bit and the second control bit is asserted,

marking the first PCI configuration space and the second PCI configuration space to indicate that the first channel control manages a first device type and the second channel control manages a second device type, the second device type being different than the first device type,

responding to configuration space accesses from an operating system by allowing access to data in the first PCI configuration space when the first control bit of the first channel control is not asserted and by allowing access to data in the second PCI configuration space requested by the operating system when the second control bit of the second channel control is not asserted,

responding to configuration space accesses by an operating system by not allowing access to data in the first PCI configuration space when the first control bit of the first channel control is asserted, and by not allowing access to data in the second PCI configuration space when the second control bit of the second channel control is asserted; and

when neither of the first control bit and the second control bit are asserted,

marking the first PCI configuration space and the second PCI configuration space to indicate that the first channel control and the second channel control manage a same device type,

responding to configuration space accesses by an operating system by allowing access to data requested by the operating system.

20. A method for configuring channels of a dual channel SCSI chip as recited in claim 19 , wherein the first channel control is a SCSI channel control and the second channel control is a RAID channel control.