Host adapter integrated data FIFO and data cache and method for improved host adapter sourcing latency
View Patent ↗A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory even though not all of the data may be cached in that memory. Hence, data is concurrently transferred to and transferred from the data FIFO/caching memory. The data transfer to the target device is throttled if cached data is unavailable in the data FIFO/caching memory for transfer, e.g., the data cache is empty for the current context.
1. A method comprising:
caching data for a context in a memory of a host adapter interfacing a first I/O bus and a second I/O bus wherein a portion of said data for said context is cached in said memory;
maintaining a queue of host adapter hardware control blocks for which said caching data is to be performed;
enabling said caching of data associated with a host adapter hardware control block following removing said host adapter hardware control block from said queue; and
transferring said portion of said data for said context from said memory concurrently with said caching data for a context in a memory caching another portion of said data for said context in said memory.
2. The method of claim 1 further comprising:
asserting a flag in said host adapter hardware control block indicating said enabling said caching of data.
3. The method of claim 1 further comprising:
maintaining an execution queue of host adapter hardware control blocks.
4. The method of claim 1 further comprising:
determining whether an enable caching flag is asserted in a host adapter hardware control block prior to initiating said transferring said data.
5. The method of claim 1 further comprising:
throttling said transferring of said data based upon whether cached data is available in said memory for transfer from said memory.
6. The method of claim 1 wherein said host adapter is a SCSI host adapter and said second I/O bus is a SCSI bus.
7. A method comprising:
maintaining a queue of host adapter hardware control blocks for which caching of data is to be performed;
removing a host adapter hardware control block from said queue upon a first I/O bus data transfer module becoming available;
enabling said first I/O bus data transfer module to transfer data specified in said host adapter hardware control block;
asserting a flag in said host adapter hardware control block indicating said enabling;
caching said data in a memory of a host adapter interfacing a first I/O bus and a second I/O bus by using said first I/O bus data transfer module to transfer said data to said memory; and
transferring said data, concurrently with said caching, from said memory.
8. The method of claim 7 further comprising:
throttling said transferring of said data based upon whether cached data is available in said memory for transfer from said memory.
9. The method of claim 7 wherein said host adapter is a SCSI host adapter and said second I/O bus is a SCSI bus.
10. A method comprising:
loading a pointer to a hardware control block in an execution queue of a host adapter interfacing a first I/O bus and a second I/O bus;
loading another pointer to said hardware control block in an enable caching queue of said host adapter;
removing said another pointer to said hardware control block from said enable caching queue upon a first I/O bus data transfer module becoming available; and
enabling said first I/O bus data transfer module to transfer data from said first I/O bus to a data first-in-first-out (FIFO)/caching memory of said host adapter following said removing said another pointer;
asserting a flag in said hardware control block to indicate said enabling said first I/o bus data transfer module;
caching data in said data FIFO/caching memory by transferring said data from said first I/O bus to said data FIFO/caching memory using said first I/O bus data transfer module following said enabling;
removing said pointer to said hardware control block from said execution queue;
determining whether said flag in said hardware control block is asserted; and
transferring said data from said data FIFO/caching memory upon said determining finding that said flag in said hardware control block is asserted.
11. The method of claim 10 further comprising:
stopping said first I/O bus data transfer module upon said determining finding that said flag in said hardware control block is unasserted.
12. The method of claim 10 wherein said host adapter is a SCSI host adapter and said second I/O bus is a SCSI bus.
13. A host adapter comprising:
a first I/O bus data transfer module;
a second I/O bus data transfer module;
a data first-in-first-out (FIFO)/caching memory coupled to said first I/O bus data transfer module and to said second I/O bus data transfer module; and
a throttle control module coupled to said first I/O bus data transfer module, to said second I/o bus data transfer module, and to said data FIFO/caching memory, wherein said throttle control module controls data transfer from said data FIFO/caching memory by said second I/O bus data transfer module as data is concurrently being transferred into said data FIFO/caching memory using said first I/O bus data transfer module.
14. The host adapter of claim 13 wherein said first I/O bus data transfer module further comprises a data-FIFO/caching-memory destination address register.
15. The host adapter of claim 14 wherein said second I/O bus data transfer module further comprises a data-FIFO/caching-memory source address register.
16. The host adapter of claim 15 wherein said throttle control module further comprises:
an empty detector coupled to said data-FIFO/caching-memory destination address register and to said data-FIFO/caching-memory source address register and having an output line coupled to said second I/O bus data transfer module.
17. The host adapter of claim 16 wherein said empty detector comprises a comparator.
18. The host adapter of claim 13 wherein said second I/O bus data transfer module further comprises a data-FIFO/caching-memory source address register.
19. The host adapter of claim 13 further comprising:
an enable caching queue.
20. The host adapter of claim 13 wherein said host adapter is a SCSI host adapter and said second I/O bus is a SCSI bus.
21. A system comprising:
a first I/O bus;
a second I/O bus; and
a host adapter comprising:
a first I/O bus data transfer module coupled to said first I/O bus;
a second I/O bus data transfer module coupled to said second I/O bus;
a data first-in-first-out (FIFO)/caching memory coupled to said first I/O bus data transfer module and to said second I/O bus data transfer module; and
a throttle control module coupled to said first I/O bus data transfer module, to said second I/O bus data transfer module, and to said data-FIFO/caching memory, wherein said throttle control module controls data transfer from said data FIFO/caching memory by said second I/O bus data transfer module as data is concurrently being transferred into said data FIFO/caching memory using said first I/O bus data transfer module.