Automatic generators for verilog programming
View Patent ↗A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
1. A computer implemented method for generating hardware description language source files, comprising:
extracting an input/output (I/O) list;
building a port list declaration file from the I/O list, the building including,
distinguishing between the variable types in the extracted input/output list; and
defining variables according to the variable types;
building a default instantiation file according to renaming rules where signal names and port names are kept constant for multiple instantiations;
interpreting coding construct to determine both I/O variable types and sizes; and
generating a sensitivity list, wherein each operation is executed by a microprocessor.
2. The method of claim 1 , wherein the variable types includes register types and wire types.
3. The method of claim 1 , wherein extracting an input/output list includes,
reading input/output variables; and
generating the port list written into a Verilog source code file.
4. The method of claim 3 , wherein the input/output list includes,
a direction and a size of the input/output variables.
5. The method of claim 1 wherein building a default instantiation file includes,
labeling port names and wire names which are obtained from the port list declaration file.
6. The method of claim 1 , wherein the sensitivity list includes a list of signals, any change to which causes execution of a section of code.
7. The method of claim 1 , wherein the port list includes,
list of signals in the input/output list.
8. The method of claim 1 , wherein the process of building a
default
instantiation file further comprising:
obtaining renaming rules from a configuration file where the rules are defined through regular expression syntax; and
applying renaming rules.
9. A computer readable storage medium for generating hardware description language source files, comprising:
program instruction for extracting an input/output (I/O) list;
program instruction for building a port list declaration file from the I/O list, the program instructions for building including,
program instruction for distinguishing between the variable types in the extracted input/output list; and
program instruction for defining variables according to the variable types;
program instruction for building a default instantiation file according to renaming rules where signal names and port names are kept constant for multiple instantiations;
program instruction for interpreting coding construct to determine both I/O variable types and sizes; and
program instruction for generating a sensitivity list.
10. The computer readable storage medium as recited in claim 9 , wherein the input/output list includes, a direction and a size of the input/output variables.