System and method for frequency and phase modulating data on a SCSI bus or a serial SCSI link
View Patent ↗A system and a method for multiplying data throughput in a SCSI bus includes identifying multiple frequencies within a bandwidth of a SCSI bus. A binary value is assigned to each one of the multiple frequencies. One of the multiple frequencies is selected. The assigned binary value of the selected frequency corresponds to a set of bits to be transmitted during a first sampling cycle. The selected frequency is transmitted on the SCSI bus during the first sampling cycle.
1. A system for multiplying data throughput in a SCSI bus comprising:
a transmitter including:
an data input;
a modulator;
a first phase locked loop (PLL) circuit, the first PLL for stabilizing a clock signal, the stabilized clock signal being coupled to the modulator;
logic for identifying a plurality of phases within a bandwidth of a SCSI bus;
logic for assigning a binary value to each one of the plurality of phases;
logic for selecting one of the plurality of phases wherein the assigned binary value of the selected phase corresponding to a plurality of bits to be transmitted during a first sampling cycle; and
logic for transmitting the selected phase on the SCSI bus during the first sampling cycle;
a receiver, the receiver being coupled to the transmitter by a SCSI bus, the receiver including:
a demodulator;
an adding circuit having a first input coupled to an output of the demodulator;
a second PLL circuit having an input coupled to the stabilized clock signal from the first PLL circuit and having an output coupled to a second input to the adding circuit;
logic for receiving the selected phase in a receiver during the first sampling cycle;
logic for identifying the selected phase;
logic for determining the corresponding assigned binary value of the selected phase; and
logic for outputting the corresponding assigned binary value of the selected phase.
2. The system of claim 1 , wherein the SCSI bus includes a parallel SCSI bus.
3. The system of claim 1 , wherein the SCSI bus includes a serial SCSI bus.
4. The system of claim 1 , wherein the plurality of phases includes 2 n phases where n is equal to the number of bits in the binary value assigned to each of the plurality of phase.
5. The system of claim 1 , wherein the plurality of phases are substantially centered about a base reference signal.
6. The system of claim 1 , wherein the selected frequency is centered in the bandwidth of the SCSI bus.
7. The system of claim 1 , wherein the plurality of phases are substantially equidistant.
8. The system of claim 7 , wherein the plurality of substantially equidistant phases includes four substantially equidistant phases.
9. The system of claim 1 , further comprising logic for applying multilevel data encoding.
10. The system of claim 1 , wherein multiplying includes double edge clocking the data.
11. A system for multiplying data throughput in a SCSI bus comprising:
a transmitter including:
a data input; and
a first phase locked loop (PLL) circuit for shifting the phase of a base reference signal according to an input signal applied to the data input;
a second PLL circuit for stabilizing a clock signal;
logic for identifying a plurality of phases within a bandwidth of a SCSI bus;
logic for assigning a binary value to each one of the plurality of phases;
logic for selecting one of the plurality of phases wherein the assigned binary value of the selected phase corresponding to a plurality of bits to be transmitted during a first sampling cycle; and
logic for transmitting the selected phase on the SCSI bus during the first sampling cycle;
a receiver, the receiver being coupled to the transmitter by a SCSI bus, the receiver including:
a third PLL circuit, the third PLL circuit for comparing a base reference signal to the phase shifted data signal output from the transmitter, the third PLL circuit having an output;
an adding circuit having a first input coupled to an output of the third PLL circuit;
a fourth PLL circuit having an input coupled to the stabilized clock signal from the second PLL circuit and having an output coupled to a second input to the adding circuit;
logic for receiving the selected phase in a receiver during the first sampling cycle;
logic for identifying the selected phase;
logic for determining the corresponding assigned binary value of the selected phase; and
logic for outputting the corresponding assigned binary value of the selected phase.
12. The system of claim 11 , wherein the SCSI bus includes a parallel SCSI bus.
13. The system of claim 11 , wherein the SCSI bus includes a serial SCSI bus.