Wired endian method and apparatus for performing the same
View Patent ↗A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be maintained in transmit order. The wired endian format is defined to allow for interfacing with both a big endian format and a little endian format. Thus, a device operating in accordance with the wired endian format is able to interface with both a device operating in accordance with the big endian format (e.g., a Serial Attached SCSI (SAS) device) and a device operating in accordance with the little endian format (e.g., a Serial ATA (SATA) device). Furthermore, since the device operating in accordance with wired endian format implements circuitry compliant with the wired endian format, duplication of circuitry to define separate data paths for interfacing with the big endian and little endian formats, respectively, is avoided.
1. An apparatus defined to communicate electronically with each of a Serial Attached SCSI (SAS) protocol device and a Serial ATA (SATA) protocol device, comprising:
a phy configured to connect the apparatus to each of the SAS protocol device and the SATA protocol device;
wired endian logic configured to communicate through the phy, the wired endian logic configured to interface a wired endian format of the apparatus with each of a big endian format of the SAS protocol device and a little endian format of the SATA protocol device; and
internal circuitry configured to operate in accordance with the wired endian format,
wherein the wired endian logic includes receipt logic including,
receiving circuitry defined to receive a sequence of bytes in a native format associated with a device from which the data sequence of bytes is to have been transmitted,
discrimination circuitry defined to identify the sequence of bytes in native format as one of a control sequence of bytes and a data sequence of bytes,
data sequence processing circuitry defined to perform receipt processing on the data sequence of bytes while in native format, the receipt processing including unscrambling of the data sequence of bytes and cyclic redundancy check data generation, and
conversion circuitry defined to convert the sequence of bytes from the native format to the wired endian format.
2. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 1 , wherein the internal circuitry configured to operate in accordance with the wired endian format is defined to store and process a sequence of bytes in transmit order.
3. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 2 , wherein the sequence of bytes is represented as a sequence of four bytes being stored in consecutive memory locations, the transmit order defined to begin with a lowest memory address associated with the sequence of bytes and progress consecutively through the remaining memory addresses associated with the sequence of bytes.
4. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 1 , wherein the wired endian logic includes transmission logic including,
discrimination circuitry defined to identify a sequence of bytes in wired endian format as one of a control sequence of bytes and a data sequence of bytes,
data sequence processing circuitry defined to convert the data sequence of bytes from the wired endian format to a native format associated with a device to which the data sequence of bytes is to be transmitted, the data sequence processing circuitry also being defined to perform pre-transmission processing on the data sequence of bytes while in native format, the data sequence processing circuitry being further defined to convert the data sequence of bytes from the native format back to the wired endian format upon completion of pre-transmission processing, and
transmission circuitry defined to transmit the sequence of bytes in wired endian format.
5. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 4 , wherein the control sequence of bytes represents one of a Serial Attached SCSI (SAS) primitive and a Serial ATA (SATA) primitive.
6. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 4 , wherein the data sequence processing circuitry is defined to represent the native format as the big endian format for the SAS protocol device and the little endian format for the SATA protocol device.
7. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 4 , wherein the pre-transmission processing includes cyclic redundancy check data generation and scrambling of the data sequence of bytes.
8. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 1 , wherein the control sequence of bytes represents one of a Serial Attached SCSI (SAS) primitive and a Serial ATA (SATA) primitive.
9. An apparatus defined to communicate electronically with each of a SAS protocol device and a SATA protocol device as recited in claim 1 , wherein the receiving circuitry is defined to represent the native format as the big endian format for the SAS protocol device and the little endian format for the SATA protocol device.