Generic packet parser
View Patent ↗A packet parser performs a multitude of compare and transition operations to parse through all layers of the networking protocol in accordance with which the packet is formed. The packet parser supports a plurality of packet encapsulation formats and uses directed distance graph syntax for graphical representation. At each node, the packet parser isolates and compares a packet header word with either a number of associated masked values or a number of ranges to find a match. Depending on the match, one of the arcs originating from that node, namely a source node, is selected for transitioning to a destination node. A pointer is incremented as transition from the source node to the destination node is made. The packet parser is adapted to make a transition to a destination node from any number of source nodes, one or more of which may be a destination node for others of these source nodes.
1. A packet parser comprising:
logic circuitry adapted to receive a first portion of a control information disposed in a packet being parsed and to transition from a first state to a second state if the first portion of the control information matches a first criteria associated with the first state;
logic circuitry adapted to receive a second portion of the control information disposed in the packet and to transition from the second state to a third state if the second portion of the control information matches a second criteria associated with the second state;
logic circuitry adapted to receive a third portion of the control information disposed in the packet and to transition from the first state to the third state if the first portion of the control information disposed in the packet matches a third criteria associated with the first state;
an offset register that is incremented if a transition from the first state to any of the second and third states is made;
logic circuitry adapted to transition from the first state to a default state if the first portion of the control information disposed in the packet does not match any one of the criteria associated with the first state;
logic circuitry adapted to transition from said default state to a fourth state;
a processor adapted to execute at least one instruction at one or more of the first, second, third, fourth and default states; wherein said processor is adapted to set a flag at one or more of the first, second, third, fourth and default states;
a memory coupled to the processor and adapted to store records associated with each parsing state and records associated with each transition originating from each parsing state; and
a plurality of comparators each coupled to the memory and each adapted to receive a record associated with a different one of the transitions originating from each parsing state.
2. The packet parser of claim 1 further comprising:
a buffer coupled to the comparators and the offset register and adapted to store the control information disposed in the packet.
3. The packet parser of claim 1 further wherein at least one of the plurality of comparators performs a masked comparison to generate a Boolean result.
4. The packet parser of claim 2 further wherein at least one of the plurality of comparators performs a range comparison to generate a Boolean result.
5. The packet parser of claim 3 further comprising:
a priority mux adapted to receive the Boolean result generated by each of the plurality of comparators and to select the Boolean result having a highest priority if more than one comparator generates a true result, said priority mux adapted to determine the address of the next records in the memory.
6. The packet parser of claim 4 further comprising:
a priority mux adapted to receive the Boolean result generated by each of the plurality of comparators and to select the Boolean result having a highest priority if more than one comparator generates a true result, said priority mux adapted to determine the address of the next records in the memory.