IP Library Granted Patent US 9,020,011
Granted Patent B1
US 9,020,011 · App. 13/902,511 · Granted Apr 28, 2015

Enabling RX signal path synchronization and alignment signals in a highly integrated TX RFIC

Inventors: Mark Hiebert (New Westminster, CA); Jay Chen (Vancouver, CA)
Assignee: PMC-Sierra US, Inc.
H04L7/02
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Quick Facts
Patent No.
US 9,020,011
App. No.
13/902,511
Granted
Apr 28, 2015
Kind
B1
Abstract

A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.

Claims (28)

1. A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver, the TX signal path circuit being responsive to a digital front end (DFE) of the MIMO transceiver for alternatively generating TX signals in a TX signal mode, or receive (RX) path phase alignment signals for phase alignment of a plurality of RX signal paths of the MIMO transceiver in a RX phase alignment mode, the TX signal path circuit comprising:

a digital up-conversion block for receiving digital baseband signals from the DFE and for generating digital intermediate frequency (IF) signals based on the digital baseband signals, the digital up-conversion block being coupled to a first numerically-controlled oscillator (NCO) for modulating the digital baseband signals to generate the digital IF signals in the TX signal mode, and further being coupled to a second NCO different from the first NCO for modulating the digital baseband signals to generate the digital IF signals in the RX phase alignment mode,

a first digital-to-analog converter (DAC) and a second DAC both coupled to the digital up-conversion block for receiving the digital IF signals and for generating analog IF signals based on the digital IF signals; and

an RF up-conversion block coupled to the first DAC and the second DAC for receiving the analog IF signals and for generating analog RF signals based on the analog IF signals, the RF up-conversion block being coupled to a TX local oscillator (LO) for modulating the analog IF signals to generate the analog RF signals in the TX signal mode, and further being coupled to a feedback (FB) LO different from the TX LO for modulating the analog IF signals to generate the analog RF signals in the RX phase alignment mode;

wherein the RF up-conversion block comprises a first divide-by-2 IQ generation (IQ-DIV2) circuit coupled to the TX LO for modulating the analog IF signals to generate the analog RF signals in the TX signal mode, and wherein the RF up-conversion block further comprises a second IQ-DIV2 circuit coupled to the FB LO for modulating the analog IF signals to generate the analog RF signals in the RX phase alignment mode, wherein the second IQ-DIV2 circuit is different from the first IQ-DIV2 circuit;

wherein the RF up-conversion block further comprises a first analog frequency mixer configured to receive the analog IF signals from the first DAC and a second analog frequency mixer configured to receive the analog IF signals from the second DAC, wherein the first analog frequency mixer and the second analog frequency mixer are both coupled to the first IQ-DIV2 circuit for generating the analog RF signals in the TX signal mode, and are both coupled to the second IQ-DIV2 circuit for generating the analog RF signals in the RX phase alignment mode;

wherein the RF up-conversion block further comprises a first multiplexer that couples the first analog frequency mixer and the second analog frequency mixer to the first IQ-DIV2 circuit in the TX signal mode, and wherein the first multiplexer couples the first analog frequency mixer and the second analog frequency mixer to the second IQ-DIV2 circuit in the RX phase alignment mode;

wherein the digital up-conversion block further comprises a first digital frequency mixer and a second digital frequency mixer both coupled to the first NCO for generating the digital IF signals in the TX signal mode, and wherein the first digital frequency mixer and the second digital frequency mixer are both coupled to the second NCO for generating the digital IF signals in the RX phase alignment mode;

wherein the digital up-conversion block further comprises a second multiplexer that couples the first NCO to the first digital frequency mixer and the second frequency mixer in the TX signal mode, and wherein the second multiplexer couples the second NCO to the first digital frequency mixer and the second digital frequency mixer in the RX phase alignment mode; and

an adder coupled to the first analog frequency mixer and the second analog frequency mixer to add the analog RF signals and to output the added analog RF signals to an amplifier for generating the TX signals in the TX signal mode or the RX path phase alignment signals in the RX phase alignment mode.

2. The TX signal path circuit according to claim 1 , wherein the first multiplexer decouples the first analog frequency mixer and the second analog frequency mixer from the first IQ-DIV2 circuit in the RX phase alignment mode.

3. The TX signal path circuit according to claim 1 , wherein the second multiplexer decouples the first NCO from the first digital frequency mixer and the second digital frequency mixer in the RX phase alignment mode.

4. The TX signal path circuit according to claim 1 further comprising a feedback circuit for monitoring RF output signals based on the TX signals in the TX signal mode, or based on the RX phase alignment signals in the RX phase alignment mode, the feedback circuit comprising the FB LO for down-converting the RF output signals.

5. The TX signal path circuit according to claim 1 , wherein the TX signal path circuit comprises a printed circuit board.

6. The TX signal path circuit according to claim 1 , wherein the TX signal path circuit comprises a radio frequency integrated circuit.

7. A multiple-input, multiple-output (MIMO) transceiver comprising a plurality of receive (RX) signal paths, a digital front end (DFE), and a transmit (TX) signal path circuit responsive to the DFE for alternatively generating TX signals in a TX signal mode, or receive (RX) path phase alignment signals for phase alignment of the plurality of RX signal paths in a RX phase alignment mode, the TX signal path circuit comprising:

a digital up-conversion block for receiving digital baseband signals from the DFE and for generating digital intermediate frequency (IF) signals based on the digital baseband signals, the digital up-conversion block being coupled to a first numerically-controlled oscillator (NCO) for modulating the digital baseband signals to generate the digital IF signals in the TX signal mode, and further being coupled to a second NCO different from the first NCO for modulating the digital baseband signals to generate the digital IF signals in the RX phase alignment mode,

a first digital-to-analog converter (DAC) and a second DAC both coupled to the digital up-conversion block for receiving the digital IF signals and for generating analog IF signals based on the digital IF signals; and

an RF up-conversion block coupled to the first DAC and the second DAC for receiving the analog IF signals and for generating analog RF signals based on the analog IF signals, the RF up-conversion block being coupled to a TX local oscillator (LO) for modulating the analog IF signals to generate the analog RF signals in the TX signal mode, and further being coupled to a feedback (FB) LO different from the TX LO for modulating the analog IF signals to generate the analog RF signals in the RX phase alignment mode;

wherein the RF up-conversion block comprises a first divide-by-2 IQ generation (IQ-DIV2) circuit coupled to the TX LO for modulating the analog IF signals to generate the analog RF signals in the TX signal mode, and wherein the RF up-conversion block further comprises a second IQ-DIV2 circuit coupled to the FB LO for modulating the analog IF signals to generate the analog RF signals in the RX phase alignment mode, wherein the second IQ-DIV2 circuit is different from the first IQ-DIV2 circuit;

wherein the RF up-conversion block further comprises a first analog frequency mixer configured to receive the analog IF signals from the first DAC and a second analog frequency mixer configured to receive the analog IF signals from the second DAC, wherein the first analog frequency mixer and the second analog frequency mixer are both coupled to the first IQ-DIV2 circuit for generating the analog RF signals in the TX signal mode, and are both coupled to the second IQ-DIV2 circuit for generating the analog RF signals in the RX phase alignment mode;

wherein the RF up-conversion block further comprises a first multiplexer that couples the first analog frequency mixer and the second analog frequency mixer to the first IQ-DIV2 circuit in the TX signal mode, and wherein the first multiplexer couples the first analog frequency mixer and the second analog frequency mixer to the second IQ-DIV2 circuit in the RX phase alignment mode;

wherein the digital up-conversion block further comprises a first digital frequency mixer and a second digital frequency mixer both coupled to the first NCO for generating the digital IF signals in the TX signal mode, and wherein the first digital frequency mixer and the second digital frequency mixer are both coupled to the second NCO for generating the digital IF signals in the RX phase alignment mode;

wherein the digital up-conversion block further comprises a second multiplexer that couples the first NCO to the first digital frequency mixer and the second frequency mixer in the TX signal mode, and wherein the second multiplexer couples the second NCO to the first digital frequency mixer and the second digital frequency mixer in the RX phase alignment mode; and

an adder coupled to the first analog frequency mixer and the second analog frequency mixer to add the analog RF signals and to output the added analog RF signals to an amplifier for generating the TX signals in the TX signal mode or the RX path phase alignment signals in the RX phase alignment mode.

8. The MIMO transceiver according to claim 7 , wherein the first multiplexer decouples the first analog frequency mixers and the second analog frequency mixer from the first IQ-DIV2 circuit in the RX phase alignment mode.

9. The MIMO transceiver according to claim 7 , wherein the second multiplexer decouples the first NCO from the first digital frequency mixers and the second digital frequency mixer in the RX phase alignment mode.

10. The MIMO transceiver according to claim 7 , wherein the TX signal path circuit further comprises a feedback circuit for monitoring RF output signals based on the TX signals in the TX signal mode, or based on the RX phase alignment signals in the RX phase alignment mode, the feedback circuit comprising the FB LO for down-converting the RF output signals.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2016
From: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 040045/0938 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC.
To: MAXLINEAR ASIA SINGAPORE PTE LTD.
Reel/Frame 039463/0743 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Apr 28, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (FORMERLY KNOW AS PMC-SIERRA US, INC.); MICROSEMI STORAGE SOLUTIONS, INC. (FORMERLY KNOW AS PMC-SIERRA, INC.)
Reel/Frame 038557/0236 →
CHANGE OF NAME Recorded Mar 22, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 038213/0291 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2013
From: HIEBERT, MARK; CHEN, JAY
To: PMC-SIERRA US, INC.
Reel/Frame 030491/0284 →