Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions
View Patent ↗Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.
1. An apparatus comprising:
a semiconductor substrate assembly;
a gate disposed on the semiconductor substrate assembly;
a first area on a first side of the gate, the first area having both salisided diffusion areas and at least one non-salisided area, wherein there is no polysilicon on the non-salisided areas;
a second area on a second side of the gate; and
contacts of the first area electrically coupled to the salisided diffusion areas, wherein at least a portion of the at least one non-salisided area is disposed between contacts of the first area that are spaced apart along a side of the gate.
2. The apparatus as defined in claim 1 , wherein the first area is for a source and the second area is for a drain.
3. The apparatus as defined in claim 1 , wherein the first area is for a drain and the second area is for a source.
4. The apparatus as defined in claim 1 , wherein the contacts comprise sets of two or more contacts each, wherein the non-salisided areas are disposed between sets of contacts that are spaced apart from each other along the side of the gate.
5. The apparatus as defined in claim 1 , wherein the second area further comprises salisided diffusion areas and at least one non-salisided area.
6. The apparatus as defined in claim 1 , further comprising ballast resistors in series with the contacts electrically coupled to the salisided diffusion areas.
7. The apparatus as defined in claim 1 , wherein the apparatus comprises an ESD snapback device.
8. The apparatus as defined in claim 1 , wherein the apparatus comprises an output driver.
9. The apparatus as defined in claim 1 , wherein at least a portion of the at least one non-salisided area is disposed in a space intersected by a line drawn between two adjacent contacts of the first area.
10. The apparatus as defined in claim 1 :
wherein the contacts of the first area comprise groups of one or more contacts, wherein each group of contacts is spaced apart along an axis orthogonal to a general direction of current flow within the first area;
wherein the at least one non-salisided area comprises a plurality of non-salisided areas, wherein at least a portion of each of the non-salisided areas is interposed in a line along the axis between two groups of one or more contacts.
11. The apparatus as defined in claim 1 , wherein the gate, the contacts, and the at least one non-salisided area are distributed across two dimensions, wherein the portion of the at least one non-salisided area that is disposed between contacts of the first area is disposed between the contacts in both dimensions.
12. An apparatus comprising:
a semiconductor substrate assembly;
an elongated gate disposed on the semiconductor substrate assembly, the elongated gate extending having an axis along its length;
a first area on a first side of the elongated gate, the first area having both salisided diffusion areas and at least one elongated non-salisided area, wherein there is no polysilicon on the elongated non-salisided areas, the at least one elongated non-salisided area having an axis along its length, wherein the axis of the at least one elongated non-salisided area is orthogonal to the axis of the elongated gate;
a second area on a second side of the elongated gate; and
contacts of the first area electrically coupled to the salisided diffusion areas, wherein the at least one non-salisided area is disposed between contacts of the first area that are spaced apart along a side of the elongated gate.
13. An apparatus comprising:
a semiconductor substrate assembly;
an elongated gate disposed on the semiconductor substrate assembly, the elongated gate extending having an axis along its length;
a first area on a first side of the elongated gate, the first area having both salisided diffusion areas and at least one non-salisided area, wherein there is no polysilicon on the non-salisided areas;
a second area on a second side of the elongated gate; and
contacts of the first area electrically coupled to the salisided diffusion areas, wherein at least a portion of the at least one non-salisided area lies directly between contacts of the first area that are spaced apart along a side of the elongated gate.