IP Library Granted Patent US 8,533,389
Granted Patent B1
US 8,533,389 · App. 12/559,951 · Granted Sep 10, 2013

Multi-client content addressable memory access control method

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Quick Facts
Patent No.
US 8,533,389
App. No.
12/559,951
Granted
Sep 10, 2013
Kind
B1
Abstract

A method and system for controlling multiple client access to cache memory and a single CAM device. Each client has a corresponding integrity controller in communication with the CAM device and all the other integrity controllers associated with the other clients in the system. Each integrity controller monitors states of the other clients, and inhibits its respective client from executing any operation when a common lookup index is detected during a co-pending operation with a first client. Once the operations of the first client are completed, its integrity controller signals the integrity controller of other clients to exit their inhibit or hold states, thereby allowing the other clients to resume their operations. Another advantage of the integrity controller is that its algorithms also prevents multiple host memory fetches of the same key, thereby saving time and improving system performance.

Claims (31)

1. A method of controlling access of at least two clients having corresponding integrity controllers to a cache memory and a content addressable memory (CAM) device, the method comprising:

detecting common lookup indices provided by the CAM device to the at least two clients in response to search requests issued by each of the at least two clients to the CAM device;

detecting a pending cache write memory operation initiated by one of the at least two clients having a corresponding first integrity controller in response to a corresponding search request; and,

inhibiting a new cache memory operation for another of the at least two clients by a corresponding second integrity controller until the pending cache write memory operation is completed in response to the common lookup indices being detected.

2. The method according to claim 1 , wherein detecting common lookup indices includes issuing a first search request of the search requests by a first client of the at least two clients.

3. The method according to claim 2 , wherein detecting common lookup indices includes issuing a second search request of the search requests by a second client of the at least two clients, after the first search request is issued.

4. The method according to claim 3 , wherein the CAM device provides a first lookup index in response to the first search request and a second lookup index in response to the second search request, the common indices including the first lookup index and the second lookup index having identical values.

5. The method according to claim 4 , wherein detecting common lookup indices includes comparing the first lookup index to the second lookup index, and providing an index match output signal when the first lookup index to the second lookup index match.

6. The method according to claim 5 , wherein inhibiting includes preventing generation of a grant signal in response to the index match output signal when the pending cache write memory operation is detected, the grant signal enabling execution of the new cache memory operation.

7. The method according to claim 3 , wherein the new cache memory operation is a read operation when the CAM device response status is a hit condition in response to the second search request.

8. The method according to claim 7 , wherein the first client reads data from the cache memory pointed to by the first lookup index, and the second client reads the data from the cache memory pointed to by the second lookup index.

9. The method according to claim 3 , wherein the cache write memory operation is a first cache write memory operation, and the new cache memory operation is a second cache write operation when the CAM device response status is a miss condition in response to the second search request.

10. The method according to claim 9 , wherein the first search request and the second search request are different.

11. The method according to claim 10 , wherein the second lookup index has the same value as the first lookup index, when the first lookup index is tagged as being least recently used.

12. The method according to claim 11 , wherein inhibiting includes enabling the second cache write operation when the first cache write memory operation is completed, the first cache write memory operation including reading data from the cache memory pointed to by the first lookup index.

13. The method according to claim 12 , wherein the second cache write memory operation includes overwriting the data from the cache memory pointed to by the first lookup index with new data, and reading the new data from the cache memory pointed to by the second lookup index.

14. The method according to claim 2 , wherein detecting a pending cache write memory operation includes initiating the pending cache write operation in response to a miss status of the first search request.

15. The method according to claim 14 , wherein initiating the pending cache write operation includes setting a write status to an active logic state.

16. The method according to claim 15 , wherein inhibiting includes preventing generation of a grant signal in response to the active logic state of the write status when the common lookup indices are detected, the grant signal enabling execution of the new cache memory operation.

17. The method according to claim 2 , wherein the pending cache write memory operation includes transferring data from a memory to the cache memory.

18. A multi-client content addressable memory (CAM) system comprising:

a content addressable memory (CAM) device providing one of a hit or a miss condition and lookup indices in response to search requests;

a cache memory for storing data addressable by the lookup indices, the cache memory executing a cache write memory operation to write new data in response to the miss condition;

at least two clients for issuing the search requests; and

an access controller inhibiting a new cache memory operation corresponding to a second client of the at least two clients until a pending cache write memory operation corresponding to a first client of the at least two clients is completed, in response to common lookup indices received by both the first client and the second client, the access controller including at least two integrity controllers each corresponding to one of the at least two clients, one of the at least two integrity controllers associated with the second client for inhibiting execution of the new cache memory operation.

19. The multi-client CAM system according to claim 18 , wherein each of the at least two integrity controllers includes inhibit circuitry for detecting the common lookup indices and an active write status of the cache memory, the inhibit circuitry preventing issuance of a grant signal enabling the new cache memory operation when the common lookup indices and the active write status are detected.

20. The multi-client CAM system according to claim 18 , wherein the inhibit circuitry includes

an index match circuit for comparing an assigned lookup index provided to a corresponding client of the at least two clients in response to a search request, against all other lookup indices provided to other clients of the at least two clients, the index match circuit providing an index match signal when the assigned lookup index matches at least one of the other lookup indices; and,

a grant circuit for preventing issuance of the grant signal to the corresponding client in response to the received index match signal and the active write status.

21. The multi-client CAM system according to claim 20 , wherein the grant circuit includes memory fetch logic for providing a fetch signal to initiate the new cache memory operation when the active write status is switched to an inactive write status, where the new cache memory operation includes a new cache write memory operation.

22. The multi-client CAM system according to claim 20 , wherein the corresponding client initiates the new cache memory operation when the corresponding grant signal is released by the grant circuit, the new cache memory operation including a new cache write memory operation.

Assignments (18)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →
CHANGE OF NAME Recorded Mar 22, 2016
From: PMC-SIERRA, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 038067/0428 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
RELEASE OF SECURITY INTEREST Recorded Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
SECURITY INTEREST IN PATENTS Recorded Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2009
From: GOYINS, GREGG; SADOWSKY, JONATHAN BRADLEY
To: PMC-SIERRA, INC.
Reel/Frame 023238/0274 →