Multi-function bypass port and port bypass circuit
View Patent ↗An architecture is provided for implementing bypass, repeater and retimer functions in high-speed multi-port SERDES bypass ports and devices. Specifically, this architecture uses clock recovery to implement a repeater function which retransmits data synchronously at a recovered-clock rate, providing very low-latency as no elastic-buffers are required to perform clock-rate compensation. It also supports a full retiming function where incoming data is retransmitted synchronously to the local-clock domain, in which case elastic-buffers are needed to compensate for differences between incoming clock and local-clock domains. The architecture disclosed herein is advantageously used for Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be leveraged in other applications like Infiniband, XAUI, PCI-Express to create a single device that be used as “eye-opener” to extend reach with low-latency when operated in “repeater mode” and as retiming device when operated as “retimer-mode”. It can also perform as an amplifier with very low-latency when operated in bypass-mode.
1. A bypass port comprising:
an input multiplexer for receiving an input from a current port input or a bypass input; a clock and data recovery (CDR) unit for receiving a data stream from the input multiplexer, and for extracting a recovered clock from the data stream;
a retimer circuit coupled to the CDR unit and for communication with an elastic buffer for retiming data to a local clock;
a retransmit multiplexer coupled to the CDR unit for retransmitting data synchronous to the recovered clock in response to data received from the CDR unit, and coupled to the retimer circuit for retransmitting data synchronous to the local clock in response to data received from the retimer circuit; and
an output multiplexer coupled to the input multiplexer for performing a bypass function in response to data received from the input multiplexer, and coupled to the retransmit multiplexer for outputting data in response to data received from the retransmit multiplexer, the output multiplexer for outputting data to a current port output or a bypass output.
2. The bypass port of claim 1 further comprising a repeater select multiplexer for monitoring a bypassed disk and for operating a disk adjacent to the monitored bypassed disk in a repeater-bypass mode.
3. The bypass port of claim 2 wherein the repeater select multiplexer is in communication with a CDR unit of a previous port and coupled to the retransmit multiplexer, for performing a repeater function in response to data received from the CDR unit of the previous port and for outputting a result to the retransmit multiplexer.
4. The bypass port of claim 2 wherein the repeater select multiplexer is coupled to the CDR unit and in communication with a retransmit multiplexer of a next port, for performing a repeater function in response to data received from the CDR unit and for outputting a result to the retransmit multiplexer of the next port.
5. The bypass port of claim 1 further comprising a digital pre-distortion filter, in communication with the CDR unit and with the retimer multiplexer, for compensating for at least one of channel inter-symbol interference and distortion.
6. The bypass port of claim 1 wherein the CDR unit comprises a digital CDR circuit.
7. The bypass port of claim 1 wherein the CDR unit comprises a digital phase locked loop (PLL) shared across a plurality of bypass ports.
8. The bypass port of claim 1 wherein the CDR unit performs clock and data recovery based on a phase-picking algorithm.
9. The bypass port of claim 1 wherein the CDR unit performs clock and data recovery based on a phase-interpolation algorithm.
10. The bypass port of claim 1 wherein the retimer circuit includes a serial in parallel out (SIPO) shift register for providing information to the elastic buffer, and a parallel in serial out (PISO) shift register for receiving information from the elastic buffer.
11. The bypass port of claim 1 wherein the retimer circuit further comprises digital logic for use in a monitoring mode.
12. The bypass port of claim 10 wherein the retimer circuit further comprises digital logic for use in a monitoring mode.
13. The bypass port of claim 12 wherein the digital logic is for receiving data from the SIPO and for monitoring the data received.
14. The bypass port of claim 12 wherein the digital logic is for sending monitoring data to the PISO for further transmission to an output of the output multiplexer.
15. A bypass port comprising:
an input multiplexer for receiving an input from a current port input or a bypass input;
a monitoring circuit for monitoring a bypassed disk based on recovered data related to the bypass disk, the monitoring circuit coupled to the input multiplexer, the monitoring circuit including:
a digital clock and data recovery (CDR) unit for receiving a data stream from the input multiplexer;
a serial in parallel out (SIPO) shift register coupled to the CDR unit; and
digital logic for receiving data from the SIPO and for monitoring the data received,
a retransmit multiplexer coupled to the monitoring circuit for retransmitting data received from the monitoring circuit; and
an output multiplexer coupled to the input multiplexer and to the monitoring circuit for performing a bypass function in response to data received from the input multiplexer, and for outputting data in response to data received from the monitoring circuit, the output multiplexer for outputting data to a current port output or a bypass output.
16. The bypass port of claim 15 wherein the monitoring circuit further includes a parallel in serial out (PISO) shift register for passing data from the digital logic to an output of the output multiplexer.
17. A port bypass circuit for connection to a plurality of disks, the port bypass circuit having a plurality of bypass ports, each of the bypass ports comprising:
an input multiplexer for receiving an input from a current port input or a bypass input; a clock and data recovery (CDR) unit for receiving a data stream from the input multiplexer, and for extracting a recovered clock from the data stream;
a retimer circuit coupled to the CDR unit for retiming data to a local clock;
a retransmit multiplexer coupled to the CDR unit for retransmitting data synchronous to the recovered clock in response to data received from the CDR unit, and coupled to the retimer circuit for retransmitting data synchronous to the local clock in response to data received from the retimer circuit; and
an output multiplexer coupled to the input multiplexer for performing a bypass function in response to data received from the input multiplexer, and coupled to the retransmit multiplexer for outputting data in response to data received from the retransmit multiplexer, the output multiplexer for outputting data to a current port output or a bypass output.
18. The port bypass circuit of claim 17 wherein the plurality of bypass ports includes every port of the port bypass circuit.
19. The port bypass circuit of claim 17 wherein the plurality of bypass ports are arranged to permit connection of the plurality of disks together in a simple loop topology.
20. A port bypass circuit for connection to a plurality of disks, comprising:
a plurality of bypass ports, each of the bypass ports including an input multiplexer for receiving an input from a current port input or a bypass input; and
a digital clock and data recovery (CDR) circuit shared across the plurality of bypass ports for receiving a data stream from the input multiplexer associated with each of the bypass ports and for extracting a recovered clock from the data stream,
each of the bypass ports further including:
a retimer circuit coupled to the digital CDR circuit for retiming data to a local clock;
a retransmit multiplexer coupled to the digital CDR circuit for retransmitting data synchronous to the recovered clock in response to data received from the digital CDR circuit, and coupled to the retimer circuit for retransmitting data synchronous to a local clock in response to data received from the retimer circuit; and
an output multiplexer coupled to the input multiplexer for performing a bypass function in response to data received from the input multiplexer, and coupled to the retransmit multiplexer for outputting data in response to data received from the retransmit multiplexer, the output multiplexer for outputting data to a current port output or a bypass output.
21. The port bypass circuit of claim 20 wherein the digital CDR circuit comprises a digital phase locked loop (PLL).
22. A port bypass method comprising:
receiving an input data stream from a current port or a previous port;
extracting a recovered clock from the data stream;
retiming data to a local clock;
retransmitting data synchronous to the recovered clock in response to a repeater condition;
retransmitting data synchronous to the local clock in response to a retimer condition;
performing a bypass function in response to a bypass condition; and
outputting data in response to data received from the retransmit multiplexer, the outputting being to a current port or a subsequent port.