Method and system for configuring an interconnect device
View Patent ↗In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storage device. Further, the system includes an initialization module to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to multiple units within the interconnect device.
1. A system for configuring an interconnect device, the system including:
a storage device to store configuration data pertaining to the interconnect device;
a configuration interface, coupled to the storage device, to request the configuration data from the storage device; and
an initialization module, coupled to the configuration interface, to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to a plurality of units coupled within the interconnect device, including a set of communication ports, an arbiter port, a functional Built-In-Self-Test (BIST) port and a management port.
2. The system of claim 1 wherein the configuration data is any one of a set of parameters pertaining to port links, a set of virtual lane parameters, security-related data, data for a Linear Forwarding Table, data for a Multicast Forwarding Table, and data for a Service Level (SL) to Virtual Lane (VL) Mapping Table.
3. The system of claim 1 wherein the storage device is an independent device.
4. The system of claim 3 wherein:
the storage device is coupled to the configuration interface via an Inter-IC (I2C) bus; and
the configuration interface comprises an I2C interface to provide access to the storage device.
5. The system of claim 4 wherein the configuration interface further includes a processor interface to communicate with a processor subsystem via a processor bus, the processor subsystem including at least a processor.
6. The system of claim 5 wherein the processor interface is to determine that the configuration data resides in the storage device, and to send a request for configuration data to the I2C interface.
7. The system of claim 5 wherein the configuration data stored in the storage device includes semaphore data to synchronize activities controlled by a processor with the configuration process.
8. The system of claim 1 wherein the storage device is part of a processor subsystem, including at least a processor.
9. The system of claim 8 wherein:
the processor subsystem is coupled to the configuration interface via a processor bus; and
the configuration interface comprises a processor interface to communicate with the processor subsystem.
10. The system of claim 8 wherein the processor subsystem includes a software driver to control accesses to the storage device.
11. The system of claim 1 further including:
a non-volatile storage device that includes an independent storage device and a storage device contained in a processor subsystem; and
wherein the configuration interface includes an Inter-IC (I2C) interface to provide access to the independent storage device and a processor interface to communicate with the processor subsystem.
12. The system of claim 11 wherein the processor interface is to determine that the configuration data resides in the independent storage device, and to send a request for configuration data to the I2C interface.
13. The system of claim 11 wherein the processor interface is to determine that the configuration data resides in the storage device contained in the processor subsystem, and to send a request for configuration data to the processor subsystem via the processor bus.
14. The system of claim 1 wherein the configuration data is stored in the storage device in blocks, each block containing an identifier of a corresponding destination unit within the interconnect device and configuration information to be loaded to the corresponding destination unit.
15. The system of claim 14 wherein the initialization module is to determine which of the plurality of units within the interconnect device should receive the configuration data using a destination unit identifier.
16. The system of claim 8 wherein the configuration data stored in the storage device includes semaphore data to synchronize activities controlled by a processor with the configuration process.
17. The system of claim 1 wherein the initialization module requests an update of the configuration data that is stored in the storage device.
18. A method for configuring an interconnect device, the method comprising:
querying a configuration interface for configuration data stored in a storage device coupled to the interconnect device;
receiving the configuration data from the configuration interface; and
distributing the configuration data to a plurality of units coupled within the interconnect device, including at least a set of communication ports, an arbiter port, a functional Built-in-Self-Test (BIST) port and a management port.
19. The method of claim 18 wherein the configuration data is any one of a set of parameters pertaining to port links, a set of virtual lane parameters, security-related data, data for a Linear Forwarding Table, data for a Multicast Forwarding Table, and data for a Service Level (SL) to Virtual Lane (VL) Mapping Table.
20. The method of claim 18 wherein:
the storage device is an independent storage device coupled to the configuration interface via an Inter-IC (I2C) bus; and
the configuration interface comprises an I2C interface to provide access to the storage device.
21. The method of claim 18 wherein:
the storage device is part of a processor subsystem, the processor subsystem including at least a processor; and
the configuration interface comprises a processor interface to communicate with the processor subsystem.
22. The method of claim 18 wherein:
the storage device includes an independent storage device and a storage device contained in a processor subsystem, the processor subsystem including at least a processor; and
the configuration interface includes an Inter-IC (I2C) interface to provide access to the independent storage device and a processor interface to communicate with the processor subsystem.
23. The method of claim 18 wherein the configuration data is stored in the storage device in blocks, each block containing an identifier of a corresponding destination unit within the interconnect device and configuration information to be loaded to the corresponding destination unit.
24. The method of claim 23 further comprising:
determining which of the plurality of units within the interconnect device should receive the configuration data using a destination unit identifier.
25. The method of claim 18 further comprising:
receiving a request to update the configuration data; and
requesting the configuration interface to update the configuration data in the storage device.
26. A system for configuring an interconnect device, the system including:
a processor subsystem including a processor and a non-volatile storage device to store configuration data pertaining to the interconnect device; and
a management port, coupled the processor subsystem via a processor bus, coupled to the storage device, to communicate with the processor subsystem, the management port comprising:
a configuration interface to send requests for the configuration data to the processor subsystem; and
an initialization module to query the configuration interface for the configuration data, to receive the configuration data from the configuration interface, and to distribute the configuration data to a plurality of units coupled within the interconnect device, including at least a set of communication ports.
27. The system of claim 26 wherein the configuration data is any one of a set of parameters pertaining to port links, a set of virtual lane parameters, security-related data, data for a Linear Forwarding Table, data for a Multicast Forwarding Table, and data for a Service Level (SL) to Virtual Lane (VL) Mapping Table.
28. The system of claim 26 wherein the plurality of units within the interconnect device further includes a functional Built-In-Self-Test (BIST) port, a management port, and an arbiter.
29. The system of claim 26 wherein the configuration interface is a processor interface.
30. The system of claim 26 wherein the processor subsystem includes a software driver to control accesses to the non-volatile storage device.
31. The system of claim 26 further comprising a non-volatile read only memory (NVRAM) coupled to the management port via an Inter-IC (I2C) bus.
32. The system of claim 31 wherein the configuration interface includes an I2C interface to provide access to the NVRAM and a processor interface to communicate with the processor subsystem.
33. The system of claim 32 wherein the processor interface is to determine that the configuration data resides in the NVRAM, and to send a request for configuration data to the I2C interface.
34. The system of claim 32 wherein the processor interface is to determine that the configuration data resides in the non-volatile storage device, and to send a request for configuration data to the processor subsystem.
35. The system of claim 26 wherein the layout of the configuration data received by the processor interface from the processor subsystem differs from the layout of the configuration data stored in the non-volatile storage device.
36. The system of claim 26 wherein the configuration data stored in the non-volatile storage device includes semaphore data to synchronize activities controlled by the processor with the configuration process.
37. A machine-readable medium storing instructions for controlling a circuit, comprising:
accessing a configuration interface to request configuration data associated with an interconnect device from a non-volatile storage device; and
accessing an initialization module to query the configuration interface for the configuration data, to receive the configuration data from the configuration interface, and to distribute the configuration data to a plurality of units coupled within the interconnect device, including a set of communication ports, an arbiter port, a functional Built-In-Self-Test (BIST) port and a management port.