Patent Assignment
Reel/Frame 042836/0046
Change of Name
Recorded: 2017-06-16
Pages: 7
Assignor
MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Executed: 2017-01-09
Assignee
MICROSEMI SOLUTIONS (U.S.), INC.
ONE ENTERPRISE, ALISO VIEJO, CALIFORNIA, 92656
Covered Properties
(138)
Fibre Channel Controller Having Both Inbound and Outbound Control Units for Simultaneously Processing Both Mutiple Inbound and Outbound Sequences
Patent:
6,425,034 →
Application:
09/183,164 →
Fibre Channel Loop Map Initialization Protocol Implemented in Hardware
Patent:
6,470,026 →
Application:
09/183,580 →
Method for Reassembling Data Frames Received-Out of Order with Respect to a Data Sequence Using Expected Frame Information and Buffer List Calculations
Patent:
6,314,477 →
Application:
09/183,865 →
Command Forwarding: a Method for Optimizing I/O Latency and Throughput in Fibre Channel Client/Server/Target Mass Storage Architectures
Patent:
6,493,750 →
Application:
09/183,969 →
Transmission of Fcp Response in the Same Loop Tenancy as the Fcp Data with Minimization of Inter-Sequence Gap
Patent:
6,463,498 →
Application:
09/183,970 →
Method and System for Negotiation of the Highest Common Link Rate Among Nodes of a Fibre Channel Arbitrated Loop
Patent:
6,477,171 →
Application:
09/452,618 →
Fibre Channel Interface Controller That Performs Non-Blocking Output and Input of Fibre Channel Data Frames and Acknowledgement Frames to and from a Fibre Channel
Patent:
6,791,989 →
Application:
09/474,945 →
Method and System for Efficient I/O Operation Completion in a Fibre Channel Node
Patent:
6,578,096 →
Application:
09/475,907 →
Method and System for Efficient I/O Operation Completion in a Fibre Channel Node Using an Application Specific Integration Circuit and Determining I/O Operation Completion Status Within an Interface Controller
Patent:
6,526,458 →
Application:
09/475,908 →
Method and System Increasing Performance Substituting Finite State Machine Control with Hardware-Implemented Data Structure Manipulation
Patent:
6,978,457 →
Application:
09/494,817 →
Mask-Based Round Robin Arbitration
Patent:
7,054,330 →
Application:
09/948,748 →
Method and Management Port for an Indirect Loop Protocol Associated with an Interconnect Device
Patent:
7,231,444 →
Application:
09/948,875 →
Method and System for Configuring an Interconnect Device
Patent:
7,043,569 →
Application:
09/948,924 →
Method and System to Manage Resource Requests Utilizing Link-List Queues Within an Arbiter Associated with an Interconnect Device
Patent:
7,237,016 →
Application:
09/949,367 →
Method and System to Allocate Resources Within an Interconnect Device According to a Resource Allocation Table
Patent:
7,150,021 →
Application:
09/977,511 →
Method and System to Map a Service Level Associated with a Packet to One of a Number of Data Streams at an Interconnect Device
Patent:
6,839,794 →
Application:
09/977,529 →
Equalization for Crosspoint Switches
Method and Apparatus to Detect a Timeout Condition for a Data Item Within a Process
Patent:
7,016,996 →
Application:
10/123,553 →
Apparatus and Methods for Increasing Bandwidth in an Infiniband Switch
Apparatus and Methods for Dynamic Reallocation of Virtual Lane Buffer Space in an Infiniband Switch
Switch-Management Agent Trap Scheme in an Infiniband-Architecture Switch
Egress Selection Switch Architecture with Power Management
Patent:
7,417,985 →
Application:
10/765,945 →
Method and System for Configuring an Interconnect Device
Serial Attached Scsi Broadcast Primitive Processor Filtering for Loop Architectures
Patent:
8,089,902 →
Application:
11/326,508 →
Data Subset Selection Algorithm for Reducing Data-Pattern Autocorrelations
Patent:
7,876,866 →
Application:
11/339,554 →
Method and Apparatus for Broadcast Primitive Filtering in Sas
Patent:
8,116,226 →
Application:
11/341,574 →
Feedback Priority Modulation Rate Controller
Method and Apparatus for Finding Subset Maxima and Minima in Sas Expanders and Related Devices
Patent:
7,958,295 →
Application:
11/389,025 →
Connection Management in Serial Attached Scsi (Sas) Expanders
Patent:
7,584,319 →
Application:
11/390,182 →
Apparatus for Interconnecting Hosts with Storage Devices
Patent:
8,127,059 →
Application:
11/470,112 →
Apparatus and Method for Detecting Extended Error Bursts
Patent:
7,802,167 →
Application:
11/669,479 →
Method and Apparatus for Extended Addressing in a Fiber Channel Arbitrated Loop
Patent:
7,860,103 →
Application:
11/693,939 →
Delay Measurements and Calibration Methods and Apparatus for Distributed Wireless Systems
Patent:
7,940,667 →
Application:
11/829,403 →
Galois Field Multiplier System and Method
Patent:
8,099,655 →
Application:
11/961,494 →
Loaded Parallel Stub Common Mode Filter for Differential Lines Carrying High Rate Digital Signals
Patent:
7,956,704 →
Application:
12/038,433 →
Lowpass-Bandstop Common Mode Filter for Differential Lines Carrying High Rate Digital Signals
Patent:
7,812,693 →
Application:
12/038,503 →
Egress Selection Switch Architecture with Power Management
Patent:
8,085,764 →
Application:
12/175,243 →
Dma Address Translation Scheme and Cache with Modified Scatter Gather Element Including Sg List and Descriptor Tables
Patent:
8,176,252 →
Application:
12/203,455 →
Semiconductor Device for Electrostatic Discharge Protection
Patent:
8,080,832 →
Application:
12/242,225 →
Logical Address Direct Memory Access with Multiple Concurrent Physical Ports and Internal Switching
Patent:
7,877,524 →
Application:
12/277,194 →
Connection Management in Serial Attached Scsi (Sas) Expanders
Patent:
8,095,722 →
Application:
12/507,859 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
Patent:
8,261,167 →
Application:
12/720,487 →
Method and System for Transporting Constant Bit Rate Clients Across a Packet Interface
Patent:
8,542,708 →
Application:
12/795,363 →
System and Method for Scatter Gather Cache Processing
Patent:
8,495,301 →
Application:
12/939,128 →
Method and Apparatus for Extended Addressing in a Fiber Channel Arbitrated Loop
Patent:
8,483,226 →
Application:
12/973,275 →
Logical Address Direct Memory Access with Multiple Concurrent Physical Ports and Internal Switching
Patent:
8,271,700 →
Application:
13/012,296 →
Management of Linked Lists Within a Dynamic Queue System
Patent:
9,262,554 →
Application:
13/027,777 →
Method and Apparatus for Queue Ordering in a Multi-Engine Processing System
Patent:
8,559,439 →
Application:
13/288,437 →
System and Method for Multiengine Operation with Super Descriptor in Sas/Sata Controller Wherein Portion of Super-Descriptor Is Executed Without Intervention of Initiator
Patent:
8,762,609 →
Application:
13/288,599 →
Methods and Apparatus for Sas Controllers with Link List Based Target Queues
Patent:
9,256,521 →
Application:
13/288,637 →
Reconfigurable Scan Chain Connectivity to Enable Flexible Device I/O Utilization
Patent:
8,533,546 →
Application:
13/309,208 →
System and Method for Algorithmic Tcam Packet Classification
Patent:
8,856,203 →
Application:
13/369,202 →
Search Table for Data Networking Matching
Patent:
9,020,953 →
Application:
13/414,383 →
Control and Coordination of Oduflex Bandwidth Resizing Operation
Patent:
8,854,963 →
Application:
13/466,679 →
Measuring Impairments of Digitized Signals in Data and Timing Recovery Circuits
Patent:
8,855,179 →
Application:
13/479,733 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
Patent:
8,386,897 →
Application:
13/483,640 →
Method of Reducing Current Leakage in a Device and a Device Thereby Formed
Timing and Data Recovery in Feed-Forward Equalization
Patent:
8,867,598 →
Application:
13/585,409 →
Method and System for Controlling Count Information in Generic Mapping Procedure
Patent:
8,848,743 →
Application:
13/689,532 →
Cyclically Interleaved Dual Bch, with Simultaneous Decode and Per-Codeword Maximum Likelihood Reconciliation
Distributed Electrostatic Discharge Protection Circuit
Patent:
9,019,669 →
Application:
13/720,048 →
Sas/Sata Store-and-Forward Buffering for Serial-Attached-Scsi (Sas) Storage Network
Patent:
8,924,610 →
Application:
13/753,255 →
Methods and Apparatus for Signal Equalization in Dual Polarization Multiplexed Optical Communication Systems
Patent:
8,923,460 →
Application:
13/767,092 →
Link Selection in a Bonding Protocol
Patent:
9,160,673 →
Application:
13/780,733 →
Method and Apparatus for Driving a Laser Diode
Patent:
9,252,563 →
Application:
13/787,351 →
Power Saving for Fifo Buffer Without Performance Degradation
Patent:
9,021,280 →
Application:
13/796,431 →
High Speed Gain and Phase Recovery in Presence of Phase Noise
Patent:
8,938,037 →
Application:
13/798,970 →
Method and Apparatus for Sampling Point Optimization
Patent:
9,020,085 →
Application:
13/803,549 →
Reed-Solomon Decoder
Patent:
9,166,623 →
Application:
13/803,919 →
Programmable Passive Peaking Equalizer
Patent:
9,225,563 →
Application:
13/826,511 →
Multi-Rate Control Loop for a Digital Phase Locked Loop
Patent:
8,964,925 →
Application:
13/827,587 →
Link Negotiation Method for Enabling Communication Between Serial Attached Small Computer Interface (Sas) Storage Devices
Patent:
8,943,233 →
Application:
13/829,367 →
System and Method for Network Switching
Patent:
9,313,563 →
Application:
13/830,231 →
Equalization Adaptation Using Timing Detector
Patent:
8,879,615 →
Application:
13/830,841 →
Multiplexing Low-Order to High-Order Odu Signals in an Optical Transport Network
Patent:
9,025,594 →
Application:
13/835,443 →
Justification Insertion and Removal in Generic Mapping Procedure in an Optical Transport Network
Patent:
8,989,222 →
Application:
13/836,100 →
Frame Delineation Method for a Generic Framing Procedure
Patent:
9,344,321 →
Application:
13/836,983 →
Demultiplexing High-Order to Low-Order Odu Signals in an Optical Transport Network
Patent:
9,288,006 →
Application:
13/837,798 →
Gfp Frame Filter
Patent:
9,374,265 →
Application:
13/839,249 →
High Bandwidth Gfp Demapper
Patent:
9,276,874 →
Application:
13/839,961 →
Self-Synchronous Scrambler / Descrambler and Method for Operating Same
Patent:
8,976,816 →
Application:
13/842,175 →
Method and System for Transporting Constant Bit Rate Clients Across a Packet Interface
Patent:
9,019,997 →
Application:
13/843,459 →
Transmitter Output Impedance Calibration for Output Rise and Fall Time Equalization and Edge Rate Control
Patent:
8,779,819 →
Application:
13/873,639 →
Systems and Methods for Clock Path Single-Ended Dcd and Skew Correction
Patent:
9,219,470 →
Application:
13/873,817 →
Transmitter Data Path Single-Ended Duty Cycle Correction for Emi Reduction
Patent:
9,071,293 →
Application:
13/873,875 →
Apparatus and Method for Modulating a Laser Beam and Sensing the Optical Power Thereof
Patent:
9,197,318 →
Application:
13/912,514 →
Method for Reducing Jitter in Receivers
Patent:
9,143,371 →
Application:
13/941,902 →
Wide-Range Fast-Lock Frequency Acquisition for Clock and Data Recovery
Patent:
9,091,711 →
Application:
13/945,596 →
Analog Finite Impulse Response Adaptation Method and Apparatus
Patent:
9,020,022 →
Application:
13/957,852 →
Windowed-Based Decision Feedback Equalizer and Decision Feedback Sequence Estimator
Patent:
8,971,396 →
Application:
13/973,849 →
Overlapping Data Integrity for Semiconductor Devices
Patent:
9,329,926 →
Application:
14/026,029 →
Method for Remapping of Allocated Memory in Queue Based Switching Elements
Patent:
9,397,961 →
Application:
14/032,557 →
Apparatus and Method for Interoperability Between Sas and Pci Express
Patent:
9,280,508 →
Application:
14/042,132 →
Method for Manufacturing Optical Engine Packages and Apparatus from Which Optical Engine Packages Are Manufactured
Patent:
9,551,845 →
Application:
14/043,720 →
Reflective Analog Finite Impulse Response Filter
Patent:
9,118,511 →
Application:
14/049,440 →
Transformer Based Circuit for Reducing Emi Radiation in High Speed Cmos Serdes Transmitters
Patent:
9,130,650 →
Application:
14/068,502 →
System and Method for Frame Alignment in High Data Rate Communication Systems
Patent:
9,444,710 →
Application:
14/086,775 →
Method and Apparatus for a Multi-Engine Descriptor Controller for Distributing Data Processing Tasks Across the Engines
Calibration Circuit for an Analog-to-Digital Converter
Patent:
8,823,563 →
Application:
14/106,836 →
System and Method for Transmitting Ancillary Data
Patent:
9,331,739 →
Application:
14/108,806 →
Threshold Voltage Adjustment in Solid State Memory
Patent:
9,224,479 →
Application:
14/132,229 →
Method and Switch for Transferring Transactions Between Switch Domains
Patent:
9,336,173 →
Application:
14/136,476 →
Method and System for Decoding Encoded Data Stored in a Non-Volatile Memory
Patent:
9,170,876 →
Application:
14/144,857 →
Compensation Factor Reduction in an Unrolled Decision Feedback Equalizer
Voltage Controlled Oscillator with Common Mode Adjustment Start-Up
Patent:
9,083,349 →
Application:
14/160,375 →
Forward Error Correction Decoder and Method Therefor
Patent:
9,325,347 →
Application:
14/186,786 →
System and Method to Achieve Datapath Latency Symmetry Through an Otn Wrapper
Patent:
9,473,261 →
Application:
14/284,110 →
Raid Enabled Nvme Device
Patent:
9,384,093 →
Application:
14/289,608 →
Apparatus and Methods for Variable Peaking and Low Pass Filtering Equalization
Patent:
9,344,300 →
Application:
14/296,412 →
Method and Controller for Requesting Queue Arbitration and Coalescing Memory Access Commands
Patent:
9,626,309 →
Application:
14/322,556 →
Measuring Impairments of Digitized Signals in Data and Timing Recovery Circuits
Patent:
9,363,046 →
Application:
14/323,856 →
High Speed Ldpc Decoder
Patent:
9,432,053 →
Application:
14/325,172 →
System and Method for Automated Test Script Generation
Patent:
9,021,440 →
Application:
14/456,996 →
Method of Reducing Current Leakage in a Product Variant of a Semiconductor Device
Patent:
9,104,825 →
Application:
14/493,157 →
Circuit and Method for Real-Time Monitoring of Process, Temperature, and Voltage Variations
Patent:
9,459,314 →
Application:
14/510,005 →
Method and System for Voltage Balancing of Multiple Rechargeable Energy Storage Devices
Patent:
9,525,298 →
Application:
14/525,967 →
Duty-Cycle Distortion Self-Correcting Delay Line
Patent:
9,257,977 →
Application:
14/581,525 →
System and Method for Boost Floor Mitigation
Patent:
9,602,133 →
Application:
14/606,579 →
Method and System for Forward Error Correction Decoding Based on a Revised Error Channel Estimate
Patent:
9,564,921 →
Application:
14/613,805 →
Apparatus and Method for Measurement of Propagation Time of a Data Stream in a Transport Network
Patent:
9,525,482 →
Application:
14/617,505 →
Forward Error Correction Decoder System
Patent:
9,473,175 →
Application:
14/618,583 →
Error Correction Code Decoder with Stochastic Floor Mitigation
Patent:
9,564,922 →
Application:
14/642,072 →
Digital Correction of Spurious Tones Caused by a Phase Detector of a Hybrid Analog-Digital Delta-Sigma Modulator Based Fractional-N Phase Locked Loop
Patent:
9,344,271 →
Application:
14/668,195 →
Shingled Magnetic Record Hard Disk Drive and Method for Creating a Logical Disk from Physical Tracks
Patent:
9,257,144 →
Application:
14/688,696 →
Memory Allocation for Raid Systems
Patent:
9,632,843 →
Application:
14/691,011 →
Distributed Electrostatic Discharge Protection Circuit
Patent:
9,391,451 →
Application:
14/697,265 →
Method for Reducing Jitter in Receivers
Patent:
9,426,004 →
Application:
14/702,508 →
Transmitter Data Path Single-Ended Duty Cycle Correction for Emi Reduction
Patent:
9,667,281 →
Application:
14/727,996 →
On-Chip Bathtub Ber Measurement for High-Speed Serdes Diagnostics
Patent:
9,444,588 →
Application:
14/739,919 →
Voltage Controlled Oscillator with Common Mode Adjustment Start-Up
Patent:
9,515,607 →
Application:
14/744,756 →
Measuring Impairments of Digitized Signals in Data and Timing Recovery Circuits
Patent:
9,331,794 →
Application:
14/755,234 →
Apparatus and Method for Modulating a Laser Beam and Sensing the Optical Power Thereof
Patent:
9,671,283 →
Application:
14/830,963 →
Method and System for Functional Verification and Power Analysis of Clock-Gated Integrated Circuits
Patent:
9,639,641 →
Application:
14/831,505 →
Method and System for Partitioning a Verification Testbench
Patent:
9,529,963 →
Application:
14/859,158 →
Method and Apparatus for Driving a Laser Diode
Patent:
9,627,848 →
Application:
14/989,276 →
Method for Manufacturing Optical Engine Packages and Apparatus from Which Optical Engine Packages Are Manufactured
Patent:
9,551,846 →
Application:
14/990,148 →
Forward Error Correction Decoder and Method Therefor
Patent:
9,467,172 →
Application:
14/991,323 →
System and Method for Transmitting Ancillary Data
Patent:
9,680,523 →
Application:
15/002,780 →
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger
Jan 21, 2010
From: PALAU ACQUISITION CORPORATION
To: PMC-SIERRA US, INC.
Reel/Frame 023828/0443 →
Merger
Jan 22, 2010
From: PALAU ACQUISITION CORPORATION
To: PMC-SIERRA US, INC.
Reel/Frame 023832/0755 →
Merger
Jan 22, 2010
From: AVAGO TECHNOLOGIES STORAGE (U.S.A.) INC.
To: PALAU ACQUISITION CORPORATION
Reel/Frame 023832/0749 →
Merger
Jan 22, 2010
From: PALAU ACQUISITION CORPORATION
To: PMC-SIERRA US, INC.
Reel/Frame 023832/0744 →
Merger
Jan 22, 2010
From: PALAU ACQUISITION CORPORATION
To: PMC-SIERRA US, INC.
Reel/Frame 023832/0707 →
Security Interest in Patents
Aug 6, 2013
From: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 030947/0710 →
Release of Security Interest
Feb 1, 2016
From: BANK OF AMERICA, N.A.
To: PMC-SIERRA, INC.; PMC-SIERRA US, INC.; WINTEGRA, INC.
Reel/Frame 037675/0129 →
Patent Security Agreement
Feb 3, 2016
From: MICROSEMI STORAGE SOLUTIONS, INC. (F/K/A PMC-SIERRA, INC.); MICROSEMI STORAGE SOLUTIONS (U.S.), INC. (F/K/A PMC-SIERRA US, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037689/0719 →
Change of Name
Mar 22, 2016
From: PMC-SIERRA US, INC.
To: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 038213/0291 →
Corrective Assignment to Correct the Name of the Assignee Previously Recorded on Reel 017207 Frame 0020. Assignor(S) Hereby Confirms the Assignment.
May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038633/0001 →
Corrective Assignment to Correct the Assignee Name Previously Recorded at Reel: 017206 Frame: 0666. Assignor(S) Hereby Confirms the Assignment.
May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
Release of Security Interest
May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
Reel/Frame 046251/0271 →