Programmable passive peaking equalizer
View Patent ↗A programmable passive peaking equalizer that can compensate for a frequency dependent loss of a variety of data channels is disclosed herein. Monotonic increase in signal loss vs. frequency of board traces, cables and even fiber causes significant distortion of transmitted data referred to as inter-symbol interference (ISI). Some embodiments of programmable passive equalizers disclosed herein can minimize ISI for a wide range of data channels with very low power penalty. Various embodiments of the passive equalizer can program the amount of peaking that occurs at the Nyquist frequency of the data rate, and hence compensates for high frequency signal loss. This in turn equalizes the high frequency patterns in the transmitted data stream, effectively eliminating the worst case ISI.
1. A programmable passive peaking equalizer comprising:
a first input port;
a first output port;
a first output capacitor coupled to the first output port and a common node;
a first inductor coupled between the first input port and the first output port;
a second inductor magnetically coupled to the first inductor, the second inductor coupled to a first variable resistance and the common node;
wherein:
when the first variable resistance is set to a first resistance value, a first voltage gain between the first input port and the first output port is at least 4 dB at a first resonance frequency of the first inductor and first output capacitor; and
when the first variable resistance is set to a second resistance value that is less than the first resistance value, a second voltage gain between the first input port and the first output port is 0 dB at the first resonance frequency of the first inductor and first output capacitor;
wherein the first and second voltage gains are measured relative to 0 Hz;
a second input port;
a second output port;
a second output capacitor coupled to the first output port and the common node;
a third inductor coupled between the second input port and the second output port;
a fourth inductor magnetically coupled to the third inductor, the fourth inductor coupled to a second variable resistance and the common node;
wherein:
when the second variable resistance is set to a third resistance value, a third voltage gain between the second input port and the second output port is at least 4 dB at a second resonance frequency determined by the second inductor and second output capacitor; and
when the second variable resistor is set to a fourth resistance value that is less than the third resistance value, a fourth voltage gain between the second input port and the second output port is 0 dB at the second resonance frequency determined by the second inductor and second output capacitor;
wherein the third and fourth voltage gains are measured relative to 0 Hz.
2. The equalizer of claim 1 , wherein at least one of the first, second, third, and fourth inductors comprise on-chip spiral inductors.
3. The equalizer of claim 1 , wherein at least one of the first and second variable resistances comprises an array of poly resistors.
4. The equalizer of claim 1 , wherein the equalizer comprises only passive elements.
5. The equalizer of claim 1 , wherein the equalizer forms a part of a receive path of a serializer-deserializer.
6. The equalizer of claim 1 , wherein the first variable resistance is programmable to any value between first and second resistance values.
7. The equalizer of claim 1 , wherein at least one of the first and second variable resistances is digitally programmable.
8. The equalizer of claim 1 , wherein the equalizer is coupled to an analog to digital converter (ADC), the ADC having a capacitance, and wherein the equalizer splits an input pad (PAD) and electrostatic discharge protection (ESD) capacitance from a large ADC capacitance.
9. The equalizer of claim 1 , wherein the equalizer is programmable to adjust the amount of any one of the first, second, third, and fourth voltage gains at a Nyquist frequency of a data rate.
10. The equalizer of claim 1 , wherein the second variable resistance is programmable to any value between third and fourth resistance values.