Method and system for decoding encoded data stored in a non-volatile memory

1. A method comprising:

storing, in a first memory, a primary codeword and a set of secondary codewords, the primary codeword comprising primary codeword data bits, each secondary codeword of the set of secondary codewords comprising data bits, wherein the data bits of each secondary codeword are a subset of the primary codeword data bits;

reading, from the first memory, the primary codeword;

decoding the primary codeword, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector comprising a LLR for each primary codeword data bit;

in response to determining that the decoding of the primary codeword is unsuccessful:

(i) reading, from the first memory, a secondary codeword of the set of secondary codewords;

(ii) decoding the secondary codeword, utilizing a hard-decision decoder, to identify and correct errored data bits in the secondary codeword and to determine a location of each errored data bit in the primary codeword;

(iii) repeating steps (i) and (ii) for all of the secondary codewords in the set of secondary codewords; and

(iv) generating an adjusted LLR vector by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

2. The method of claim 1 , wherein adjusting a LLR for each primary codeword data bit comprises increasing the LLR for each primary codeword data bit at the determined locations of the errored data bits.

3. The method of claim 2 , wherein adjusting a LLR for each primary codeword data bit comprises decreasing the LLR for each primary codeword data bit not at the determined locations of the errored data bits.

4. The method of claim 1 , further comprising:

decoding the primary codeword, utilizing the soft-decision decoder, based on the adjusted LLR vector; and

in response to determining that the decoding of the primary codeword is unsuccessful, repeating steps (i)-(vi) until the decoding of the primary codeword based on the adjusted LLRs is successful or a number of iterations exceeds a predetermined value.

5. The method of claim 1 , wherein the primary codeword is a low-density parity-check (LDPC) codeword.

6. The method of claim 1 , wherein each secondary codeword in the set of secondary codewords is a Reed-Solomon (RS) codeword.

7. The method of claim 1 , wherein each secondary codeword in the set of secondary codewords is an erasure codeword.

8. The method of claim 7 , wherein decoding the secondary codeword further comprises decoding the erasure codeword, utilizing the hard-decision decoder, to identify data bits marked as erasures in the erasure codeword and to determine a location of each data bit marked as an erasure in the primary codeword, and wherein generating an adjusted LLR vector further comprises setting the LLR to zero for each primary codeword data bit at the locations the erased data bits.

9. The method of claim 1 , further comprising, reading, from a second memory, the second memory being a non-volatile memory, utilizing a second memory reader, the primary codeword and the set of secondary codewords.

10. A non-transitory computer-readable medium comprising computer-readable instructions executable by a processor to perform the method of claim 1 .

11. A system comprising:

a first memory storing a primary codeword and a set of secondary codewords, the primary codeword comprising primary codeword data bits, each secondary codeword of the set of secondary codewords comprising data bits, wherein the data bits of each secondary codeword are a subset of the primary codeword data bits; and

a processor operably coupled to the first memory and configured to:

read, from the first memory, the primary codeword;

decode the primary codeword, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector comprising a LLR for each primary codeword data bit;

in response to a determination that the decoding of the primary codeword is unsuccessful:

(i) read, from the first memory, a secondary codeword of the set of secondary codewords;

(ii) decode the secondary codeword, utilizing a hard-decision decoder, to identify and correct errored data bits in the secondary codeword and to determine a location of each errored data bit in the primary codeword;

(iii) repeat steps (i) and (ii) for all the secondary codewords in the set of secondary codewords; and

(iv) generate an adjusted LLR vector by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

12. The system of claim 11 , further comprising:

a second memory storing the primary codeword and the set of secondary codewords, the second memory being a non-volatile memory;

a second memory reader operably coupled to the first memory and the second memory, the second memory reader configured to read and store the primary codeword and the set of secondary codewords in the first memory.

13. The system of claim 11 , wherein the processor is further configured to increase the LLR for each primary codeword data bit at the determined locations of the errored data bits.

14. The system of claim 13 , wherein the processor is further configured to decrease the LLR for each primary codeword data bit not at the determined locations of the errored data bits.

15. The system of claim 12 , wherein the processor is further configured to:

decode the primary codeword, utilizing the soft-decision decoder, based on the adjusted LLR vector; and

in response to a determination that the decoding of the primary codeword is unsuccessful, repeat steps (i)-(vi) until the decoding of the primary codeword based on the adjusted LLRs is successful or a number of iterations exceeds a predetermined value.

16. The system of claim 11 , wherein the primary codeword is a low-density parity-check (LDPC) codeword.

17. The system of claim 11 , wherein each secondary codeword in the set of secondary codewords is a Reed-Solomon (RS) codeword.

18. The system of claim 11 , wherein each secondary codeword in the set of secondary codewords is an erasure codeword.

19. The system of claim 18 , wherein the processor is further configured to:

decode the erasure codeword, utilizing the hard-decision decoder, to identify erased data bits in the erasure codeword and to determine a location of each erased data bit in the primary codeword; and

set the LLR to zero for each primary codeword data bit at the locations the erased data bits.