Method and management port for an indirect loop protocol associated with an interconnect device
View Patent ↗A method and management port for an indirect loop protocol associated with an interconnect device. In one embodiment, a method to handle a request sent to an interconnect device includes receiving the request at a destination switch from a host network adapter; generating a response to the request in the destination switch; and returning the response to the host network adapter, wherein the destination switch includes a management port for addressing the interconnect device that implements an indirect loop protocol.
1. A method to handle a request sent to an interconnect device, the method comprising:
receiving the request at a decoder of a management port;
determining a performance requirement associated with the request;
routing the request to an agent to execute the request when the performance requirement matches an agent's performance capability; and
routing the request to a microprocessor interface when the performance requirement does not match the agent's performance capability.
2. The method of claim 1 , further comprising:
routing the request to a microprocessor from the microprocessor interfaces;
processing the request by the microprocessor;
generating a response by the microprocessor;
routing the response to the microprocessor interface; and
routing the response from the interface to a requesting node.
3. The method of claim 2 , further comprising:
disabling the agent when the agent's performance capability does not match the performance requirement.
4. The method of claim 1 , further comprising:
routing the request to a microprocessor from the microprocessor interface;
altering the performance requirement to match the agent's performance capability to generate a second request;
routing the second request to the microprocessor interface from the microprocessor;
receiving the second request at the decoder;
routing the second request to the agent;
processing the second request at the agent;
generating a first response by the agent;
routing the first response to the microprocessor;
altering the first response by the microprocessor to generate a second response; and
routing the second response to the requesting node.
5. The method of claim 4 , wherein the first response is a first trap packet, and wherein the second response is a second trap packet.
6. A system to handle a request sent to an interconnect device comprising:
means for receiving the request at a decoder of a management port;
means for determining a performance requirement associated with the request;
means for routing the request to an agent to execute the request when the performance requirement matches an agent's performance capability; and
means for routing the request to a microprocessor interface when the performance requirement does not match the agent's performance capability.
7. The system of claim 6 , further comprising:
means for routing the request to a microprocessor from the microprocessor interfaces;
means for processing the request by the microprocessor;
means for generating a response by the microprocessor;
means for routing the response to the microprocessor interface; and
means for routing the response from the interface to a requesting node.
8. The system of claim 7 , further comprising:
means for bypassing the agent when the agent's performance capability does not match the performance requirement.
9. The system of claim 6 , further comprising:
means for routing the request to a microprocessor from the microprocessor interface;
means for altering the performance requirement to match the agent's performance capability to generate a second request;
means for routing the second request to the microprocessor interface from the microprocessor;
means for receiving the second request at the decoder;
means for routing the second request to the agent;
means for generating a first response by the agent;
means for routing the first response to the microprocessor;
means for altering the first response by the microprocessor to generate a second response; and
means for routing the second response to the requesting node.
10. The system of claim 9 , wherein the first response is a first trap packet, and wherein the second response is a second trap packet.
11. A computer-readable medium having stored thereon a plurality of instructions, said plurality of instructions when executed for handling a request sent to an interconnect device by a computer, cause said computer to perform:
receiving the request at a decoder of a management port;
determining a performance requirement associated with the request;
routing the request to an agent to execute the request when the performance requirement matches an agent's performance capability; and
routing the request to a microprocessor interface when the performance requirement does not match the agent's performance capability.
12. The computer-readable medium of claim 11 having stored thereon additional instructions, said additional instructions when executed by a computer, cause said computer to further perform:
routing the request to a microprocessor from the microprocessor interfaces;
processing the request by the microprocessor;
generating a response by the microprocessor;
routing the response to the microprocessor interface; and
routing the response from the interface to a requesting node.
13. The computer-readable medium of claim 12 having stored thereon additional instructions, said additional instructions when executed by a computer, cause said computer to further perform:
bypassing the agent when the agent's performance capability does not match the performance requirement.
14. The computer-readable medium of claim 11 having stored thereon additional instructions, said additional instructions when executed by a computer, cause said computer to further perform:
routing the request to a microprocessor from the microprocessor interface;
altering the performance requirement to match the agent's performance capability to generate a second request;
routing the second request to the microprocessor interface from the microprocessor;
receiving the second request at the decoder;
routing the second request to the agent;
processor the second request at the agent;
generating a response by the agent;
routing the response to the microprocessor;
altering the response by the microprocessor to generate a second response; and
routing the second response to the requesting node.
15. The computer-readable medium of claim 14 , wherein the first response is a first trap packet, and wherein the second response is a second trap packet.
16. A management port for an interconnect device, comprising:
a decoder for receiving requests for managing the interconnect device, the decoder implementing an indirect loop protocol;
a microprocessor interface coupled to the decoder;
one or more agents coupled to the decoder; and
a data bus interconnecting the decoder, microprocessor interface, and agents, wherein the requests comprise:
a request for the performance measurements of the interconnect device;
a request for the status of one or more ports within the interconnect device; and
a request for the diagnosis of an arbiter within the interconnect device.
17. The management port of claim 16 , wherein the agents comprise:
a sub-network management agent;
a baseboard management agent;
a performance management agent; and
a sub-network trap management agent.
18. The management port of claim 17 , wherein the management port generates a routing table with local IDs each associated with a plurality of interconnect devices.
19. The management port of claim 17 , wherein the decoder:
determines a performance requirement associated with the request;
routes the request to an agent to execute the request when the performance requirement matches an agent's performance capability of the agent; and
routes the request to the microprocessor interface when the performance requirement does not match the agent's performance capability.
20. The management port of claim 19 , wherein the microprocessor interface provides the request to a microprocessor and receives a response packet from the microprocessor.
21. A machine-readable medium having embodied thereon a description of a circuit in a hardware description language, the description comprising a series of instructions which, when executed by a processor, synthesize a circuit comprising:
a decoder for receiving requests for managing an interconnect device, the decoder implementing an indirect loop protocol;
a microprocessor interface coupled to the decoder;
one or more agents coupled to the decoder; and
a data bus interconnecting the decoder, microprocessor interface, and agents.
22. The machine-readable medium of claim 21 wherein the description includes a behavioral level description of the circuit.
23. The machine-readable medium of claim 22 wherein the behavioral level description is compatible with a VHDL format.
24. The machine-readable medium of claim 23 wherein the behavioral level description is compatible with a Verilog format.
25. The machine-readable medium of claim 21 wherein the description includes a register transfer level netlist.
26. The machine-readable medium of claim 21 wherein the description includes a transistor level netlist.