Duty-cycle distortion self-correcting delay line
A duty-cycle distortion self-correcting delay line has an even number of programmable delay lines connected in series between a data signal input and a data signal output. Each programmable delay line is paired with a corresponding inverting element. A data signal propagated from the input to the output is passed un-inverted in half of the delay lines and is passed inverted in the other half of the delay lines. When the data signal is a square wave clock signal, a duty cycle distortion caused by the delay lines passing the un-inverted signal is cancelled by a duty cycle distortion caused by the delay lines passing the inverted signal. The inverting elements may be XNOR or XOR gates connected to an anti-aging signal input which, when asserted, maintains all of the delay lines in order to avoid differential aging effects leading to acquired duty cycle distortion.
1. A delay line comprising a data signal input, a data signal output, and, connected in series between the data signal input and the data signal output:
a first programmable delay line;
a first inverting element following the first programmable delay line;
a second programmable delay line following the first inverting element; and
a second inverting element either preceding the first programmable delay line or following the second programmable delay line.
2. The delay line according to claim 1 further comprising a control signal input connected to the first programmable delay line and the second programmable delay line selectively to engage a first number of delay elements in the first programmable delay line and a second number of delay elements in the second programmable delay line.
3. The delay line according to claim 2 , wherein the first number of delay elements is equal to the second number of delay elements.
4. The delay line according to claim 2 , wherein the first number of delay elements is unequal to the second number of delay elements.
5. The delay line according to claim 4 , wherein the first number of delay elements differs from the second number of delay elements by one delay element.
6. The delay line according to claim 2 , wherein each additional delay element is engaged alternatively in the first programmable delay line and the second programmable delay line.
7. The delay line according to claim 1 , wherein the first inverting element is a first inverter and the second inverting element is a second inverter.
8. The delay line according to claim 1 , wherein the first inverting element is a first XNOR gate, and the second inverting element is a second XNOR gate.
9. The delay line according to claim 8 further comprising an anti-aging signal input connected to a respective input of each of the first XNOR gate and the second XNOR gate.
10. The delay line according to claim 9 , wherein, when an anti-aging signal is asserted on the anti-aging signal input, the first XNOR gate and the second XNOR gate respectively hold the first programmable delay line and the second programmable delay line in a common state.
11. The delay line according to claim 9 , wherein, when an anti-aging signal is not asserted on the anti-aging signal input, the first XNOR gate and the second XNOR gate each function as inverters.
12. The delay line according to claim 1 , wherein the first inverting element is a first XOR gate, and the second inverting element is a second XOR gate.
13. The delay line according to claim 12 further comprising an anti-aging signal input connected to an inverter connected to a respective input of each of the first XOR gate and the second XOR gate.
14. The delay line according to claim 13 , wherein, when an anti-aging signal is asserted on the anti-aging signal input, the first XOR gate and the second XOR gate respectively hold the first programmable delay line and the second programmable delay line in a common state.
15. The delay line according to claim 13 , wherein, when an anti-aging signal is not asserted on the anti-aging signal input, the first XOR gate and the second XOR gate each function as inverters.
16. The delay line according to claim 1 , wherein the first programmable delay line and the second programmable delay line are identical in circuit structure and layout.
17. A delay line comprising a data signal input, a data signal output, and, connected in series between the data signal input and the data signal output, an even number of programmable delay lines all either preceded by or followed by respective corresponding inverting elements.
18. The delay line according to claim 17 further comprising a control signal input connected to each of the programmable delay lines selectively to engage respective numbers of delay elements in the programmable delay lines.
19. The delay line according to claim 18 , wherein the control signal input is configured to engage each additional delay element in a ring pattern.
20. A method of controlling the delay line according to claim 18 , the method comprising asserting a control signal on the control signal input to engage each additional delay element in the delay line in a ring pattern.