Method and system for configuring an interconnect device
View Patent ↗In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storage device. Further, the system includes an initialization module to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to multiple units within the interconnect device.
1. A method for configuring an interconnect device, the method comprising:
requesting configuration data;
determining whether the requested configuration data resides in an independent storage device coupled to the interconnect device via an Inter-IC (I2C) bus or a storage device contained in a processor subsystem coupled to the interconnect device via a processor bus;
sending a request for the configuration data to the I2C if the requested configuration data is determined to reside in the independent storage device, or to the processor sub-system if the requested configuration data is determined to reside in the storage device;
receiving the configuration data from the determined one of the independent storage device or the storage device; and
communicating the configuration data to an initialization module for distribution to a plurality of units within the interconnect device.
2. The method of claim 1 wherein the configuration data is any one of a set of parameters pertaining to port links, a set of virtual lane parameters, security-related data, data for a Linear Forwarding Table, data for a Multicast Forwarding Table, and data for a Service Level (SL) to Virtual Lane (VL) Mapping Table.
3. The method of claim 1 wherein the plurality of units within the interconnect device includes a set of communication ports, a functional Built-In-Self-Test (BIST) port, a management port, and an arbiter.
4. The method of claim 1 wherein the storage device is an independent device coupled to the interconnect device via an Inter-IC (I2C) bus.
5. The method of claim 1 wherein the storage device is part of a processor subsystem coupled to the interconnect device via a processor bus.
6. The method of claim 1 wherein the configuration data is stored in the storage device in blocks, each block containing an identifier of a corresponding destination unit within the interconnect device and configuration information to be loaded to the corresponding destination unit.
7. The method of claim 1 further comprising:
receiving a request to update the configuration data stored in the storage device; and
transferring update data to the storage device.
8. A system for configuring an interconnect device, the system comprising:
a non-volatile random access memory (NVRAM) to store configuration data pertaining to the interconnect device;
a processor subsystem including a processor; and
a management port comprising:
a configuration interface comprising a processor interface coupled to the processor subsystem via a processor bus, and coupled to an I2C interface to provide access to the NVRAM, the configuration interface determining whether requested configuration data resides in the NVRAM or the processor subsystem, and sending a request for the configuration data to the processor subsystem or the I2C interface in accordance with the determination; and
an initialization module to query the configuration interface for the requested configuration data, to receive the configuration data from the configuration interface, and to distribute the configuration data to a plurality of units within the interconnect device.
9. The system of claim 8 wherein the configuration data is any one of a set of parameters pertaining to port links, a set of virtual lane parameters, security-related data, data for a Linear Forwarding Table, data for a Multicast Forwarding Table, and data for a Service Level (SL) to Virtual Lane (VL) Mapping Table.
10. The system of claim 8 wherein the plurality of units within the interconnect device includes a set of communication ports, a functional Built-In-Self-Test (BIST) port, a management port, and an arbiter.
11. The system of claim 8 wherein the NVRAM is a serial electrically erasable programmable read only memory (SEEPROM).
12. The system of claim 8 wherein the configuration data stored in the NVRAM includes semaphore data to synchronize activities controlled by the processor with the configuration process.
13. The system of claim 8 wherein the configuration data is stored in the NVRAM in blocks, each block containing an identifier of a corresponding destination unit within the interconnect device and configuration information to be loaded to the corresponding destination unit.
14. The system of claim 13 wherein the layout of the configuration data received by the initialization module is the same as the layout of the configuration data stored in the NVRAM.