Method of reducing current leakage in a device and a device thereby formed
View Patent ↗A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the V t (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high V t circuit, a standard V t circuit, a low V t circuit, and an SRAM cell V t circuit.
1. A method of fabricating a semiconductor device for reducing current leakage therein, the method comprising:
obtaining a design for fabricating the semiconductor device, the design comprising active circuits and one or more unused circuits, wherein obtaining comprises:
identifying, by a processor, at least one of the one or more unused circuits in the obtained design of the semiconductor device based on a set of timing constraints by:
applying a subtractive unused circuit identification;
analyzing static timing of all active circuits for determining a first circuit list including at least one timing-constrained circuit having a timing-constrained path;
generating a second circuit list of at least one non-timing-constrained circuit by omitting circuits in the first circuit list from a list of all circuits; and
identifying, in the second circuit list, the at least one of the one or more unused circuits in the device by omitting, from the second circuit list, circuits remaining in operation in the semiconductor device;
fabricating the semiconductor device based on the obtained design;
during fabrication:
selectively masking the semiconductor device to expose the at least one of the one or more unused circuits; and
modifying a characteristic of each exposed unused circuit to inhibit the each exposed unused circuit and to reduce current leakage therefrom.
2. The method of claim 1 , wherein the design comprises a plurality of unused circuits each having the same device type, and
wherein selectively masking the semiconductor device comprises masking the plurality of unused circuits of the same device type with a circuit mask distinctive to the device type.
3. The method of claim 1 , wherein the design comprises a plurality of unused circuits, and the plurality of unused circuits comprises a first set of unused circuits of a first device type and a second set of unused circuits of a second device type, and
wherein selectively masking comprises:
masking the first set of unused circuits with a first circuit mask; and
masking the second set of unused circuits with a second circuit mask;
the first and second unused circuit masks being distinctive to the first and second device type, respectively.
4. The method of claim 1 , wherein the design comprises a plurality of unused circuits, the plurality of unused circuits comprises a plurality of analog circuits, and selectively masking the semiconductor device comprises selectively masking the plurality of analog circuits.
5. The method of claim 1 , wherein the design comprises a plurality of unused circuits, the plurality of unused circuits comprises a plurality of digital circuits, and selectively masking the semiconductor device comprises selectively masking the plurality of digital circuits.
6. The method of claim 1 , wherein modifying the characteristic of the each exposed unused circuit comprises:
modifying an electrical characteristic of each exposed unused circuit, resulting in each exposed unused circuit having modified electrical properties.
7. The method of claim 1 , wherein modifying the characteristic of each exposed unused circuit comprises:
modifying a physical characteristic of each exposed unused circuit, resulting in each exposed unused circuit having modified electrical properties.
8. The method of claim 1 , wherein modifying the characteristic of each exposed unused circuit comprises implanting a dopant.
9. The method of claim 8 , wherein implanting the dopant comprises implanting at least one custom dopant.
10. The method of claim 9 , wherein the at least one custom dopant comprises at least one of: a voltage threshold (Vi) implant, a pocket implant, a lightly doped drain (LDD) implant, and a source and drain implant.
11. The method of claim 1 , wherein modifying the characteristic of each exposed unused circuit comprises at least one of: modifying a gate dielectric thickness; and modifying a gate length.
12. The method of claim 11 wherein modifying the characteristic of each exposed unused circuit comprises modifying a gate length, and wherein modifying a gate length comprises:
at least one of modifying a poly critical dimension (CD), modifying a gate spacer dimension, and modifying a FinFET fin width.
13. The method of claim 1 , wherein identifying comprises identifying the at least one of the one or more unused circuits in the obtained design of the semiconductor device based on a set of timing constraints.
14. The method of claim 1 , wherein analyzing comprises scanning the at least one timing-constrained circuit with a DC scanning technique.
15. The method of claim 1 , wherein analyzing comprises analyzing static timing of all active circuits using a set of timing constraints for the semiconductor device, thereby providing static timing circuit data including data relating to the at least one timing-constrained circuit.
16. The method of claim 15 , further comprising:
reanalyzing static timing of all active circuits; and
performing, utilizing a processor, at least one of a circuit level simulation and a gate level timing simulation for confirming that the semiconductor device, fabricated based on the obtained design, is fully functional.
17. The method of claim 1 , wherein identifying includes applying a marker layer for tagging the at least one identified unused circuit.
18. The method of claim 1 , further comprising preparing a new set of timing models for all types of circuits that are identified as unused circuits.
19. The method of claim 1 , further comprising:
selecting an exception circuit from the at least one identified unused circuit; and
maintaining power to the exception circuit, providing the exception circuit with a minimized current leakage, and rendering the exception circuit operable at a minimized speed.
20. A semiconductor device fabricated by a method comprising:
obtaining a design for fabricating the semiconductor device, the design comprising active circuits and one or more unused circuits, wherein obtaining comprises:
identifying, by a processor, at least one of the one or more unused circuits in the obtained design of the semiconductor device based on a set of timing constraints by:
applying a subtractive unused circuit identification;
analyzing static timing of all active circuits for determining a first circuit list including at least one timing-constrained circuit having a timing-constrained path;
generating a second circuit list of at least one non-timing-constrained circuit by omitting circuits in the first circuit list from a list of all circuits; and
identifying, in the second circuit list, the at least one of the one or more unused circuits in the device by omitting, from the second circuit list, circuits remaining in operation in the semiconductor device;
fabricating the semiconductor device based on the obtained design;
during fabrication:
selectively masking the semiconductor device to expose the at least one of the one or more unused circuits; and
modifying a characteristic of each exposed unused circuit to inhibit each exposed unused circuit and to reduce current leakage therefrom.
21. A semiconductor device fabricated by a method comprising:
obtaining a design for fabricating the semiconductor device, the design comprising active circuits and a plurality of unused circuits, and the plurality of unused circuits comprises a first set of unused circuits of a first device type and a second set of unused circuits of a second device type, wherein obtaining comprises:
identifying, by a processor, at least one of the one or more unused circuits in the obtained design of the semiconductor device based on a set of timing constraints by:
applying a subtractive unused circuit identification;
analyzing static timing of all active circuits for determining a first circuit list including at least one timing-constrained circuit having a timing-constrained path;
generating a second circuit list of at least one non-timing-constrained circuit by omitting circuits in the first circuit list from a list of all circuits; and
identifying, in the second circuit list, the at least one of the one or more unused circuits in the device by omitting, from the second circuit list, circuits remaining in operation in the semiconductor device;
fabricating the semiconductor device based on the obtained design;
during fabrication:
selectively masking the semiconductor device to expose the at least one of the one or more unused circuits, wherein selectively masking comprises:
masking the first set of unused circuits with a first circuit mask; and
masking the second set of unused circuits with a second circuit mask;
the first and second unused circuit masks being distinctive to the first and second device type, respectively; and
modifying a characteristic of each exposed unused circuit to inhibit each exposed unused circuit and to reduce current leakage therefrom.