Method and system for partitioning a verification testbench
View Patent ↗A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.
1. A method of testing a design under test (DUT) using a verification test bench, the method comprising:
obtaining a computer-readable source code of the DUT and a computer-readable source code of the verification test bench;
separating the computer-readable source code of the verification test bench into reactive components and analytic components, the reactive components for sending test traffic to the DUT and for receiving test traffic from the DUT, the analytic components for verifying the test traffic between the reactive components and the DUT;
compiling, at a computer processor, the reactive components and the computer-readable source code of the DUT into a first computer-executable test bench;
compiling, at the computer processor, the analytic components into a second computer-executable test bench;
running the first computer-executable test bench on a simulator program of the computer processor to generate test traffic between the reactive components and the DUT;
separately running the second computer-executable test bench on the simulator program of the computer processor to verify the test traffic; and
outputting an indication of whether the second computer-executable test bench verified the test traffic as a successful simulation of the DUT or as a failed simulation of the DUT.
2. The method of claim 1 , further comprising separating the analytic components based on specific programming language constructs.
3. The method of claim 1 , further comprising separating the analytic components based on an analysis of information flow within the source code.
4. The method of claim 1 , further comprising:
separating the computer-readable source code of the verification test bench into a first orthogonal portion of the analytic components;
separating the computer-readable source code of the verification test bench into a second orthogonal portion of the analytic components;
compiling, at the computer processor, the first orthogonal portion of the analytic components into a third computer-executable test bench;
compiling, at the computer processor, the second orthogonal portion of the analytic components into a fourth computer-executable test bench;
running the third computer-executable test bench on the simulator program of the computer processor; and
running the fourth computer-executable test bench on the simulator program of the computer processor separately from the third computer-executable test bench.
5. The method of claim 1 , further comprising:
recording the test traffic generated from the first computer-executable test bench simulation; and
providing the test traffic to the second computer-executable test bench simulation to verify the test traffic.
6. The method of claim 5 comprising:
storing the recorded test traffic; and
iteratively updating the analytic components and providing the stored test traffic to the second computer-executable test bench simulation, in order to improve the verification of the test traffic.
7. A method of testing a design under test (DUT) using a verification test bench, the method comprising:
obtaining a computer-readable source code of the DUT and a computer-readable source code of the verification test bench;
separating the computer-readable source code of the verification test bench into reactive components and analytic components, the reactive components for sending test traffic to the DUT and for receiving test traffic from the DUT, the analytic components for verifying the test traffic between the reactive components and the DUT;
compiling, at a computer processor, the reactive components and the computer-readable source code of the DUT into a first computer-executable test bench;
compiling, at the computer processor, the analytic components into a second computer-executable test bench;
running the first computer-executable test bench on a hardware emulator apparatus to generate test traffic between the reactive components and the DUT;
separately running the second executable test bench on the hardware emulator apparatus to verify the test traffic; and
outputting an indication of whether the second computer-executable test bench verified the test traffic as a successful simulation of the DUT or as a failed simulation of the DUT.
8. The method of claim 7 , further comprising:
recording the test traffic generated from the first computer-executable test bench emulation; and
providing the test traffic to the second computer-executable test bench emulation to verify the test traffic.
9. The method of claim 8 , further comprising:
storing the recorded test traffic; and
iteratively updating the analytic components and providing the stored test traffic to the second computer-executable test bench emulation, in order to improve the verification of the test traffic.