Method of reducing current leakage in a product variant of a semiconductor device
View Patent ↗A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the V t (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The semiconductor process technique is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for unused circuits having previously applied semiconductor process techniques, such as a high V t circuit, a standard V t circuit, a low V t circuit, and an SRAM cell V t circuit.
1. A method of reducing current leakage in a product variant of a semiconductor device, the method comprising:
obtaining a design for fabricating the semiconductor device, the design comprising active circuits and unused circuits;
identifying, from the unused circuits in the obtained design, one or more idle circuits, wherein each idle circuit is an unused circuit that is idle and not used in the product variant of the semiconductor device;
fabricating the product variant of the semiconductor device based on the obtained design; and
during fabrication of the product variant of the semiconductor device:
selectively masking the product variant of the semiconductor device to expose each identified idle circuit; and
modifying a characteristic of each exposed identified idle circuit to inhibit each exposed identified idle circuit and to reduce current leakage therefrom.
2. The method of claim 1 , wherein identifying further comprises identifying, from the unused circuits in the obtained design, one or more idle circuits using design analysis on the product variant of the semiconductor device.
3. The method of claim 1 , wherein identifying further comprises identifying, from the unused circuits in the obtained design, one or more idle circuits using function simulation on the product variant of the semiconductor device.
4. The method of claim 1 , wherein identifying further comprises identifying, from the unused circuits in the obtained design, one or more idle circuits using hardware emulation on the product variant of the semiconductor device.
5. The method of claim 1 , wherein identifying further comprises applying a subtractive idle circuit identification to identify, from the unused circuits in the obtained design, one or more idle circuits.
6. The method of claim 5 , wherein applying the subtractive idle circuit identification comprises performing a static timing analysis on the active circuits and the unused circuits in the obtained design by using a predetermined set of timing constraints for the product variant of the semiconductor device.
7. The method of claim 1 , wherein identifying further comprises:
analyzing static timing of all active circuits defined by the product variant of the semiconductor to generate a timing-constrained circuit list comprising one or more timing-constrained active circuits that have a timing-constrained path;
generating a non-timing constrained circuit list comprising one or more non-timing-constrained active circuits by omitting the one or more active circuits that have a timing constrained-path from a list of all active and unused circuits in the obtained design.
8. The method of claim 7 , further comprising identifying the one or more idle circuits in the obtained design by omitting active circuits remaining in operation in the product variant of the semiconductor device from the non-timing constrained circuit list.
9. The method of claim 8 , further comprising applying a scan-based test to the fabricated product variant, wherein the scan-based test is the same scan-based test applied to the semiconductor device.
10. The method of claim 7 , wherein analyzing comprises analyzing static timing of all circuits defined by the product variant of the semiconductor device by using a set of timing constraints for the product variant, thereby providing static timing circuit data including data relating to each of the one or more timing-constrained active circuits.
11. The method of claim 9 , further comprising:
reanalyzing static timing of all active circuits; and
performing, utilizing a processor, at least one of a circuit level simulation and a gate level timing simulation for confirming that the fabricated product variant of the semiconductor device is fully functional.
12. The method of claim 1 , wherein identifying further comprises applying a marker layer for tagging the one or more idle circuits.
13. The method of claim 1 , further comprising verifying a configuration of the product variant of the semiconductor device and preparing a new set of timing models for all types of unused circuits that are identified as idle circuits.
14. The method of claim 1 , further comprising:
selecting an exception circuit from the one or more idle circuits; and
maintaining power to the exception circuit, providing the exception circuit with a minimized current leakage, and rendering the exception circuit operable at a minimized speed.
15. The method of claim 1 , wherein the one or more idle circuits comprise a plurality of idle circuits each having the same device type, and wherein selectively masking the product variant of the semiconductor device comprises masking the plurality of idle circuits of the same device type with an idle circuit mask distinctive to the device type.
16. The method of claim 1 , wherein the one or more idle circuits comprise a plurality of idle circuits, wherein the plurality of idle circuits comprise a first set of idle circuits of a first device type and a second set of idle circuits of a second device type, and wherein selectively masking comprises:
masking the first set of idle circuits with a first idle circuit mask; and
masking the second set of idle circuits with a second idle circuit mask; and
the first and second idle circuit masks being distinctive to the first and second device type, respectively.
17. The method of claim 1 , wherein modifying further comprises:
modifying an electrical characteristic of each exposed idle circuit, resulting in each exposed idle circuit having modified electrical properties.
18. The method of claim 1 , wherein modifying further comprises:
modifying a physical characteristic of each exposed idle circuit, resulting in each exposed idle circuit having modified electrical properties.
19. The method of claim 1 , wherein modifying the characteristic of each exposed idle circuit comprises implanting a dopant.
20. The method of claim 18 , wherein the dopant comprises at least one of: a voltage threshold (Vt) implant, a pocket implant, a lightly doped drain (LDD) implant, and a source and drain implant.
21. The method of claim 1 , wherein modifying the characteristic of each exposed idle circuit comprises at least one of modifying a gate dielectric thickness or modifying a gate length.